Re: multiple analog blocks

Hi Geoffrey,

>
> A major benefit of Verilog-A (over VHDL-AMS) is, in fact, that it *is*
> a proper language, with a well-defined subset defined in the LRM.

Given that this is the case, one thing I've always wanted to see in
Verilog-A is a robust mechanism for opening/closing/reading/writing files.
To this end, it seems that it would be nice to have well-defined initial
(and maybe final?) blocks that only execute "once" and not during each
iteration of the newton solver (like @(initial_step)). For file
operations, this would be very beneficial I think.

Also, I don't believe that $fscanf is technically a part of the Verilog-A
subset. Should it be formally incorporated at some point...?

- Boris