Re: multiple analog blocks

Geoffrey.Coram wrote:
> edaorg@v-ms.com wrote:
>   
>> I see you're still stuck with the idea that analog or digital owns
>> something rather than it being shared.
>>     
>
> Seeing as how this is stated in 8.2 Fundamentals (actually, 8.2.2)
> in the mixed signal chapter of the LRM, I think you can't just
> say it's a bad mental picture.
>   
It is bad. It follows from the thinking that an AMS simulator is really 
two simulators tied loosely together rather than a fully integrated 
piece of software. That thinking is old and leads to bad algorithmic 
decisions, e.g. the port-bound A/D conversion rather than process bound 
(because that matched someone's old implementation).

Since we were addressing the particular case where variables are 
assigned permanent values at initialization, there is no requirement 
that the analog process be able to write them anyway (allowed by 8.2.2).

The meaning of "The domain of a variable is that of the context from 
which its value is assigned." in 8.2.2 is not clear, and variables don't 
actually need to be assigned a domain, only drivers and receivers need 
to be considered as belonging a domain, but there is no real reason you 
can't assign to "analog" objects in a digital process or "digital" 
objects from an analog.

8.2.2 probably needs some refinement: what you want to avoid is race 
conditions or other indeterminate results.  Section 9.3.2.1 addresses 
part of that and the implication of the algorithm in 9.3.4 is that 
digital and analog are not evaluated concurrently so I think the 
indeterminism is fairly limited.

>> I didn't think Verilog-A was a proper language now that Verilog-AMS is
>> out, and any half decent simulator should be able to read a bunch of
>> variable assignment statements in a simple  initial-begin-end block even
>> if it can't do the rest of the digital stuff.
>>     
>
> A major benefit of Verilog-A (over VHDL-AMS) is, in fact, that it *is*
> a proper language, with a well-defined subset defined in the LRM.
>   
Not really, the fact that OVI agreed to let Verilog-A exist as an 
intermediate step has led to people treating it as a standalone 
language, but it was never meant to exist for long. The original goal 
was to have a single AMS language. Ken campaigned for the subset 
approach and after the Verilog-A LRM was released he and the other 
Cadence representatives on this committee went to great lengths to stall 
the process of releasing a Verilog-AMS LRM. That's why SystemVerilog is 
now a separate standard off at the IEEE without any analog capability.
> There are a number of analog-only simulators, whether internal to
> semiconductor companies or developed by smaller EDA companies that
> don't want/need to spend the time implementing all the digital stuff --
> particularly when this whole exercise would be a distraction from what
> really needs to be done, in terms of generating a robust dependency tree.
>   
I'm sure that anyone who has an "analog only" Verilog-AMS simulator 
would not be daunted by having to parse initial blocks.

What do you mean by "a robust dependency tree"?

Kev.
> -Geoffrey
>
>