Re: multiple analog blocks

> Geoffrey,
> relying on compiler optimization to extract the initialization
> statements
> does lead to other issues (beyond work for the compiler implementator!).
>
> In some situations it is not possible for the optimizer to figure out
> what the user wants.
> Putting once off calculations in some kind of initial block makes the
> intent much
> clearer to compiler (and probably to others who read the model as well).
>
> Two examples to consider are;
>
> Example 1:
>
> module foo;
> parameter h = 6;
>
> real y;
>
> analog begin
>   y = h^2;
>   if (y > 12.3) $strobe ("warning y is out-of-range");
> ...
> endmodule
>
> The LRM requires that the warning would be printed every timestep but
> this may not be what the user
> intends, because y is just dependent on a parameter and maybe the user
> just wants the calculation of y and the warning to be printed just once.
>   

I hate to add another question to all this but I can't help myself and I 
saw it mentioned in a previous email from someone. Why is it that we are 
not allowing variable initialisation when declaring analog variable?

With this we could then simply use constant functions and then we have a 
ready to go method to perform complex pre-simulation initialisation.
Example 1 could be:
module foo
parameter h = 6;

analog function real check_range;
    input val, threshold
    real val, threshold;
    begin
       check_range = val^2;
       if(val > threshold) $strobe("warning val is out-of-range");
    end
endfunction

real y = check_range(h, 12.3);
analog begin
    ...
endmodule

And example 2 would simply be:
real out = $random();

Dave

-- 
=====================================
-- David Miller
-- Design Technology (Austin)
-- Freescale Semiconductor
-- Ph : 512 996-7377 Fax: x7755
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