Hi Kevin >> >> But for a given timestep, the simulator solves each instance through >> a set of iterations using the previous timestep's converged values as >> a starting point. Lets assume that it does 2 iterations, and that P >> == 1 (I didn't mean to have 0). If it solves each instance in some >> seemingly random order, maybe due to parallel processing, then on the >> first iteration, we load a potential contribution between circuit >> nodes a and b of 5 volts. On the second iteration, we happen to solve >> instance top last, hence we load a flow of 0 between a and b. This is >> going to mean that we won't converge, so it does possibly another >> iteration and gets a different answer and so on. >> This is a problem isn't it? > > No, each analog block is independent, top always contributes a flow of > 0.0 and other always a potential of 5 (if P is true). > >> While writing this, I am assuming that the hierarchical reference is >> the same as if you had it in the same analog block (hence the >> sequential nature applies), i.e. >> analog begin >> I(a,b) <+ 0; >> if(P) >> V(a,b) <+ 5; >> end > > Why would you do that? > >> >> on iteration one. And then on iteration two >> analog begin >> if(P) >> V(a,b) <+ 5; >> >> I(a,b) <+ 0; >> end >> >> Is this the wrong way to look at hierarchical contributions. > > Yep. > > It's just a connection made directly rather than through a port. Post > elaboration the is no need for the simulator to differentiate between > connections by OOMR and connections via ports. There are some issues > of syntax and how to attribute a discipline to an OOMR and where to > insert A/D convertors - but they're not major. > > IMO you should be able to describe your design without connecting any > ports and just wire it all up with OOMRs and it should behave the same. > Okay so you are saying that out of module reference V(top.a,top.b) is simply creating a new unnamed branch between ckt nodes a, and b. This branch will be in parallel to any unamed branches between (a,b) that exist in module top. I was of the understanding that out of module reference had to reference a pre-existing branch. If that's not the case then I understand how this all works. This then means that you can only ever have a switch branch that ca possibly switch from potential to flow in the same instance. But then I have to wonder what happens if instead of unnamed branches, the user try's to contribute to a named branch using an out of module reference. Surely this then would mean it is accessing the same branch (not creating one in parallel) and hence all the problems I was discussing above become an issue since order that instances are evaluated can change results. Or would this also be a separate branch? Dave > Kev. > >> >> Dave >> > > -- ===================================== -- David Miller -- Design Technology (Austin) -- Freescale Semiconductor -- Ph : 512 996-7377 Fax: x7755 ===================================== -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Jan 2 20:06:38 2007
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