Re: Verilog-AMS Committee Meeting Minutes - Dec 22 2006

From: Geoffrey.Coram <Geoffrey.Coram_at_.....>
Date: Wed Jan 03 2007 - 05:03:08 PST
Dave Miller wrote:
> 
> Okay so you are saying that out of module reference V(top.a,top.b) is
> simply creating a new unnamed branch between ckt nodes a, and b. This
> branch will be in parallel to any unamed branches between (a,b) that
> exist in module top.

This doesn't seem right to me; the LRM specifically says that
there is at most *one* unnamed branch between two nodes.
If module top has only named branches, then the OOMR would
create a new unnamed branch.

-Geoffrey

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Received on Wed Jan 3 05:03:59 2007

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