Dave Miller wrote: > Hi Kevin >> .... >> >> IMO you should be able to describe your design without connecting any >> ports and just wire it all up with OOMRs and it should behave the same. >> > Okay so you are saying that out of module reference V(top.a,top.b) is > simply creating a new unnamed branch between ckt nodes a, and b. This > branch will be in parallel to any unamed branches between (a,b) that > exist in module top. I was of the understanding that out of module > reference had to reference a pre-existing branch. If that's not the > case then I understand how this all works. This then means that you > can only ever have a switch branch that can possibly switch from > potential to flow in the same instance. Same analog block (rather than instance), that would be my understanding, but the LRM may not be saying that. > But then I have to wonder what happens if instead of unnamed branches, > the user tries to contribute to a named branch using an out of module > reference. Surely this then would mean it is accessing the same branch > (not creating one in parallel) and hence all the problems I was > discussing above become an issue since order that instances are > evaluated can change results. Or would this also be a separate branch? I think we have two distinct meanings for "branch", one is the syntactic declaration of a node-pair, the other is the "mathematical" one in the matrix used to solve the circuit. The latter is just the contribution from a particular analog block to a node-pair. We might want consider rewording some of the LRM to make it clearer. Kev. > > Dave >> Kev. >> >>> >>> Dave >>> >> >> > > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Jan 3 15:26:56 2007
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