Re: Verilog-AMS Committee Meeting Minutes - Dec 22 2006

edaorg@v-ms.com wrote:
> >
> > "It is illegal to contribute to an external switch branch from within an
> > analog block."
> >
> > [ Presumably, this means to contribute via a hierarchical out-of-module
> > reference. ]
> >
> >
> IMO the statement in 5.3.13 is fairly meaningless: there is no way
> from within a module that you can tell that a branch you are
> connecting to is a switch branch in some other module (doesn't
> matter if it's OOMR or not). So if it is illegal it's going to be a
> elaboration/runtime error, but personally I see no reason for it to
> be illegal. I'd vote for striking the sentence.

If you name the branch in the module:
  branch (p,n) br1;
  I(br1) <+ 2.0;
and then use this OOMR:
  V(top.br1) <+ 3.0;

then you are trying to change the type of branch (flow source
or potential source).

I believe the same problem exists if the branch is unnamed
in both places, since the LRM specifically states there is
only one unnamed branch between two nodes.

Obviously, if the module uses the name (br1) and the OOMR
uses V(top.p,top.n) then these are different branches, and
the simulator should have no problem with it, just as you
can put a current source and a voltage source in parallel.

But you can't make the same analogy when the contributions
are to the same branch.

-Geoffrey

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