Re: Verilog-AMS Committee Meeting Minutes - Dec 22 2006

From: Kevin Cameron <kevin_at_.....>
Date: Wed Jan 03 2007 - 14:55:02 PST
Geoffrey.Coram wrote:
> edaorg@v-ms.com wrote:
>   
>> IMO you should be able to describe your design without connecting any
>> ports and just wire it all up with OOMRs and it should behave the same.
>>     
>
> If you did so, then wouldn't you have to have a separate module
> for every instance in the design?  Ports allow me to have a gate
> defined once but instantiated multiple times to connect different
> nets.  I guess it would behave the same, but that's an odd way
> to work.
>
> -Geoffrey
>   
I wasn't recommending it as a methodology :-)

Kev.

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.
Received on Wed Jan 3 14:55:26 2007

This archive was generated by hypermail 2.1.8 : Wed Jan 03 2007 - 14:56:26 PST