Re: Verilog-AMS Committee Meeting Minutes - Dec 22 2006

From: Geoffrey.Coram <Geoffrey.Coram_at_.....>
Date: Wed Jan 03 2007 - 05:19:25 PST
edaorg@v-ms.com wrote:
> 
> IMO you should be able to describe your design without connecting any
> ports and just wire it all up with OOMRs and it should behave the same.

If you did so, then wouldn't you have to have a separate module
for every instance in the design?  Ports allow me to have a gate
defined once but instantiated multiple times to connect different
nets.  I guess it would behave the same, but that's an odd way
to work.

-Geoffrey

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Received on Wed Jan 3 05:20:10 2007

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