-----Original Message----- From: owner-verilog-ams@server.eda.org [mailto:owner-verilog-ams@server.eda.org] On Behalf Of Kevin Cameron Sent: Wednesday, January 03, 2007 2:55 PM To: verilog-ams@server.eda.org Cc: Geoffrey.Coram Subject: Re: Verilog-AMS Committee Meeting Minutes - Dec 22 2006 Geoffrey.Coram wrote: > edaorg@v-ms.com wrote: > >> IMO you should be able to describe your design without connecting any >> ports and just wire it all up with OOMRs and it should behave the same. >> > > If you did so, then wouldn't you have to have a separate module > for every instance in the design? Ports allow me to have a gate > defined once but instantiated multiple times to connect different > nets. I guess it would behave the same, but that's an odd way > to work. > > -Geoffrey > I wasn't recommending it as a methodology :-) Kev. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Jan 3 15:00:10 2007
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