Re: disallow distributed switch branches

Geoffrey.Coram wrote:
> Kevin Cameron wrote:
>   
>> Marq Kole wrote:
>>     
>>> owner-verilog-ams@server.eda.org wrote on 18-04-2007 22:52:38:
>>>       
>>>> If
>>>>  The behavior of an analog blocks should not change if they
>>>>  are moved from separate modules into the same module.
>>>> holds, then
>>>>  If you contribute to the potential of a branch in two analog
>>>>  blocks, the values add; if you put the analog contrib
>>>>  statements into separate modules, the potentials are in parallel.
>>>> is untrue.
>>>>         
>>> Then one should conclude that the above proposition (The behavior ...
>>> same module) is false.
>>>       
>> From a programmers perspective it is extremely bad to have the same
>> piece of code do different thing in different contexts - a guaranteed
>> source of bugs.
>>     
>
> But I think your proposal has the same problem.  If I have
>   analog begin
>     begin : bl1
>       V(a,b) <+ 5;
>     end
>     begin : bl2
>       V(a,b) <+ 6;
>     end
>   end
> then personally I think it would be confusing if adding
> "end analog begin" before the second block were to change the
> behavior.  We have two voltage contribs; under the present
> standard, if they are in the same module, then they add; if
> they are in different modules, then they are in parallel.
> There's no way to be consistent with both when allowing
> multiple analog blocks in one module.
>   
You are confusing the issues. The problem is if you have

   module A ...
       electrical a,b;
       analog  V(a,b) <+ 5;
       analog  V(a,b) <+ 6;
   endmodule

Which would work under Marq's proposed rules giving V(a,b) == 11, but if 
you split it into submodules:

   module A ...
       electrical a,b;
       B;
       C;
  endmodule

  module B..
       analog  V(A.a,A.b) <+ 5;
  endmodule
  module C
       analog  V(A.a,A.b) <+ 6;
  endmodule

That fails because the contributions are now considered as being in 
parallel.

If the branches are switch branches instead then you would expect the 
latter case to fail _iff_ both submodules drive voltage at the same 
time. However the single module case would not fail (under the Marq's 
rules) since the contributions would just add.

Marq's solution to this problem is to ban the switch branches, mine is 
to not use summing semantics between analog blocks in  the same module 
unless explicitly told to do so.

> I think that multiple analog blocks is more similar to
> multiple sequential blocks in a single analog statement.
> Further, Ken's inductor with series resistance example
> gives us an explicit example where we want this behavior.
>   
I'm not disagreeing with the requirement, just the proposed solution.
> Your goal of "multiple analog blocks equivalent to
> multiple modules" would be a nice goal, if it weren't
> incompatible with other goals.
>   
I'm not seeing which goal it's in conflict with. Using concatenated 
blocks gives the user the choice of summing or non-summing behavior 
(under my rules) - for the example above the following would work as 
Marq intends:

   module A ...
       electrical a,b;
       analog  concatenate sum_v V(a,b) <+ 5;
       analog  concatenate sum_v V(a,b) <+ 6;
   endmodule

- while the original will work as I intend.

My point being: Ken's requirement is satisfied by concatenating blocks, 
so using summing behavior as the default in a module (rather than 
parallel) is unnecessary, and will only cause confusion.

Kev.

> -Geoffrey
>   


-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.