Re: disallow distributed switch branches

Kevin Cameron wrote:
> Marq Kole wrote:
> > owner-verilog-ams@server.eda.org wrote on 18-04-2007 22:52:38:
> > > If
> > >  The behavior of an analog blocks should not change if they
> > >  are moved from separate modules into the same module.
> > > holds, then
> > >  If you contribute to the potential of a branch in two analog
> > >  blocks, the values add; if you put the analog contrib
> > >  statements into separate modules, the potentials are in parallel.
> > > is untrue.
> >
> > Then one should conclude that the above proposition (The behavior ...
> > same module) is false.
> 
> From a programmers perspective it is extremely bad to have the same
> piece of code do different thing in different contexts - a guaranteed
> source of bugs.

But I think your proposal has the same problem.  If I have
  analog begin
    begin : bl1
      V(a,b) <+ 5;
    end
    begin : bl2
      V(a,b) <+ 6;
    end
  end
then personally I think it would be confusing if adding
"end analog begin" before the second block were to change the
behavior.  We have two voltage contribs; under the present
standard, if they are in the same module, then they add; if
they are in different modules, then they are in parallel.
There's no way to be consistent with both when allowing
multiple analog blocks in one module.

I think that multiple analog blocks is more similar to
multiple sequential blocks in a single analog statement.
Further, Ken's inductor with series resistance example
gives us an explicit example where we want this behavior.
Your goal of "multiple analog blocks equivalent to
multiple modules" would be a nice goal, if it weren't
incompatible with other goals.

-Geoffrey

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