Cross keyword in System Verilog

So there was some discussion in the call last night when Stuart mentioned that 
'cross' is a keyword in System Verilog as well and I mentioned I would take a 
look at the syntax to see if this clash would cause a problem from the 
compiler's point of view.

This is obviously one construct that we don't want to change in Verilog-AMS 
(like we did for 'logic') as 'cross' is widely used to say the least.

In System Verilog, the 'cross' keyword is used when defining cover groups. I 
don't understand exactly what this means from a language point of view - I am 
just looking at the syntax.

There doesn't appear that there would be any reason for Verilog-AMS event 
statements to be allowed inside a coverage_spec (since digital events aren't).

The example in the P1800 LRM does include a digital event as part of the 
covererage event:

   bit [3:0] a, b;
   covergroup cov @(posedge clk);
     aXb : cross a, b;
   endgroup

So I guess there is a chance that we may want to also allow our analog events 
there, although as I said, I don't understand exactly how these covergroup's 
are used:
   covergroup cov @(cross(V(clk));
     aXb : cross a, b;
   endgroup

but even in this case, these two uses can be easily distinguished by a compiler 
as the context is different.
So there doesn't seem to be any reason from a compiler/parsing perspective why 
the Verilog-AMS 'cross', and the SV 'cross' can't live side by side.

But as mentioned last night, it might be good if we compile a list of 
Verilog-AMS keywords and send to the System Verilog working group. This way 
when they add new keywords, they at least look at this list and possibly use an 
alternative in the case of conflicts.

Cheers...
Dave

-- 
=====================================
-- David Miller
-- Design Technology (Austin)
-- Freescale Semiconductor
-- Ph : 512 996-7377 Fax: x7755
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