Re: Draft 2 is now available - 7.10

Since the semantics in other LRMs are clearly wrong for the purpose of 
AMS (http://www.eda-stds.org/verilog-ams/hm/2378.html),
here's another suggestion for the sentence in 7.10:

	For the purposes of driver access functions and connect module insertion, 
        a driver of a signal is a process which assigns a value to the signal, or
        a connection of the signal to an output port of a simulation primitive.


Kev.


Kevin Cameron wrote:
>
>     Section 7.10 says -
>
>         A driver of a signal is a process which assigns a value to the
>         signal, or a connection of the signal to
>         an output port of a module instance or simulation primitive.
>
>     I think it should just say -
>
>         A driver of a signal is a process which assigns a value to the
>         signal, or a connection of the signal to
>         an output port of a simulation primitive.
>
>     Output ports on regular modules are not in themselves drivers just
>     connections to drivers. The implication of the current text is that you
>     would count all the ports through a hierarchy down to a process or
>     primitive as separate drivers.
>


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