Re: Verilog-AMS committee meeting reminder - 3rd April 2008

Marq Kole wrote:
>
> Hi Kevin,
>
> I currently cannot oversee all implications of this attribution of 
> connect modules. In my limited view I think a better description of 
> what happens for all connect module resolutions is needed: merged vs. 
> split, and regular vs. detailed resolution. A change in connect rules 
> could very well imply that the hierarchical references to the connect 
> module instances change. I would suggest that hierarchical references 
> to connect rules be invariant to these rules as much as possible.
>

This proposal does not change what gets connected/converted, just the 
location of the connect module instance - which (as you say) can move 
around anyway due to rule/design changes.

If you want an invariant path to connect modules instances I would 
suggest adding an array of aliases attached to the net e.g.:

    <path>.<signal>.connect[<index>]

- where <path>.<signal>.connect[0] will be a reference to a connect 
module instance, which you could query for more information.

Kev.

>
> Just my $0.02...
>
> Perhaps we can take this up in the mixed-signal subcommittee?
>
> Cheers,
> Marq
>
> owner-verilog-ams@server.eda.org wrote on 02-04-2008 20:48:00:
>
> > Sri Chandra wrote:
> > > 06:30am US Pacific
> > > ...
> > Not going to make that.
> > >
> > > Agenda:
> > > * Review of draft3 from chapter 5 onwards.
> >
> > I didn't get any feedback on on the connect module placement issue -
> >
> >     http://www.verilog.org/mantis/view.php?id=2343
> >
> > Does anyone have problems with making the changes?
> >
> > Kev.
> >
> > >
> > > Marq - Would it be possible for you to chair the call tomorrow 
> please?
> > > I  may not be able to join the call.
> > >
> > > cheers,
> > > Sri
> >
> >
> > --
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> > Tel: (650) 949 3400 Ext 3415
> >
> >
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