Re: Verilog-AMS committee meeting reminder - 3rd April 2008

David Miller wrote:
> Kevin Cameron wrote:
>> David Miller wrote:
>>>> I didn't get any feedback on on the connect module placement issue -
>>>>
>>>>    http://www.verilog.org/mantis/view.php?id=2343
>>>>
>>>> Does anyone have problems with making the changes?
>>> Hello Kevin,
>>> I am trying to get an understanding of this proposal. Consider a 
>>> simple module setup:
>>>
>>> module parent();
>>>   electrical a;
>>>   electrical gnd;
>>>   ground gnd;
>>>   wire net;
>>>
>>>   vdc #(.dc(5)) v0(a,gnd);
>>>   mydig d1(a,net);
>>> endmodule
>>>
>>> module mydig(in,out);
>>>   wire in; input in;
>>>   wire out; output out;
>>>   assign out = in;
>>> endmodule
>>>
>>>
>>> Currently the connect module (a2d) to convert the electrical net 'a' 
>>> to digital  'in' is inserted in parent.
>>> Are you proposing that it is inserted in mydig instead?
>>
>> Yes, since the "assign" statement is the actual driving process.
>>
>
> But then that will mean I will insert more connect modules than 
> potentially needed.
> If my parent module instantiates 2 different digital modules
>   mydig_1 d1(a,net);
>   mydig_2 d2(a,net);
>
> that both take the continuous net 'a' as an input. In today's flow 
> this would result in 1 connect module being inserted in 'parent' and 
> that output from that connect module being passed to d1 and d2.
> But this new proposal will result in 2 connect modules being inserted, 
> one in both d1 and d2.

Different problem. As I said to Marq: I'm not changing the rules about 
what gets converted/connected, just the location of the connect module 
instance.

>
> I can see that this is the required behaviour if modules mydig_1 and 
> mydig_2 have different power supplies but if they don't then this 
> becomes inefficient. Also if the connect module is inserted in the 
> child module, there is an overhead on the implementation to change all 
> references to the original net 'in' to the output from the connect 
> module.

The references changes are pretty much the same which ever way you do it.

>
> My preference would be to address this problem as well as how to 
> correctly support multiple power supplies and power sensitive connect 
> modules post LRM2.3  in the sub-committee along with the other mixed 
> signal changes.

I would like to have this fixed ASAP before people get used to it being 
wrong, the rest of the back-annotation/power-supply stuff is just 
extensions that can be done later.

Kev.

>
> Dave
>
>> Kev.
>>
>


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