Hmm ... the semicolon can't be required since it wasn't there in LRM 2.1 or 2.2. In the call, we decided to make it optional in A.1.6 nature nature_identifier [ : parent_nature ] [ ; ] and A.1.7 discipline discipline_identifier [;] We did not explicitly say whether to update all the items in Annex D.1; it sounds like we want to move towards consistency with the other items (module, connect_rules, etc. have the ;) so therefore we should add ; to all the natures and disciplines, with the understanding that all simulators need to update their parsers to handle the new optional semicolon. Also, we missed Graham's second point; I think we should have guard directives for D.3: `ifdef DRIVER_ACCESS_VAMS `else `define DRIVER_ACCESS_VAMS 1 ... `endif -Geoffrey Graham Helwig wrote: > Hello Sri and others, > > Here is some feedback about draft 4: > > Annex D.1 has not semicolon after the discipline and nature names. > > Should Annex D.3 (driver_access.vams file) have guard directives like > disciplines.vams and constant.vams? > > Regards > Graham > > Sri Chandra wrote: >> The draft4-preliminary version has been uploaded: >> >> http://www.eda.org/verilog-ams/htmlpages/public-docs/VAMS_v2.3-Draft4-preliminary.pdf >> >> >> We will review this on Monday evening 7:00am Pacific. I am hoping that >> this will be the last major draft version before we submit to the >> board for approval. We will make minor edits based on the review but >> no new features, enhancements or major corrections. this will have to >> wait probably till the next version and needs to be captured in >> Mantis. Hopefully by mid/late next week we can finalize on LRM2.3 >> version. >> >> Please find call times and details: >> >> Date: 12 May 2008 (Monday) >> >> Call-In Details: >> USA Toll Free: 877-346-8823 >> USA Toll: +1-203-320-0407 >> Passcode: 602538 >> >> Call times: >> 07:00am US Pacific >> 09:00am US Central >> 10:00am US Eastern >> 16:00pm Eindhoven >> 19:30pm Noida >> 23:30pm Adelaide >> >> Regards, >> Sri >> >> >> Sri Chandra wrote: >>> Stu, >>> >>> Thanks for getting back immediately. If there aren't any changes to >>> draft4 then i guess I can put pressure on Accellera to make a press >>> release (assuming we send it to the board immediately), otherwise we >>> need to find a different way of publicizing it at DAC. >>> >>> >>> All, >>> So if its okay with everybody I guess we can have a review of that >>> document tomorrow (May 9th), same time at the various timezones. >>> Please let me know if there are any concerns otherwise for this week >>> we will meet on Friday morning pacific time 7:00am. Please consider >>> this as the agenda reminder. :) If for any reason, Stu is unable to >>> send the doc, we will meet next week. >>> >>> Regards, >>> Sri >>> >>> Stuart Sutherland wrote: >>>> Sri, >>>> >>>> I got side-tracked last week by some unexpected business and some >>>> family >>>> affairs. I was not able to work on the editing for draft 4 last >>>> week, but >>>> started work on it this week. I expect to have draft 4 completed by >>>> 5 PM >>>> Pacific time today (Thursday, May 8). >>>> >>>> I would think Accellera could still squeeze in doing a press release >>>> -- DAC >>>> is still 30 days away, as of today. >>>> >>>> I can be available for a conference call Thursday evening or anytime on >>>> Friday (Pacific time). >>>> >>>> I will be at DAC. >>>> >>>> Stu >>>> ~~~~~~~~~~~~~~~~~~~~~~~~~ >>>> Stuart Sutherland >>>> stuart@sutherland-hdl.com >>>> +1-503-692-0898 >>>> >>>>> -----Original Message----- >>>>> From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On >>>>> Behalf Of Sri Chandra >>>>> Sent: Wednesday, May 07, 2008 11:42 PM >>>>> To: Stuart Sutherland; Verilog-AMS LRM Committee >>>>> Subject: Draft 4 version >>>>> >>>>> >>>>> Stu, >>>>> >>>>> Would you able to give an estimate when this would be ready? I guess >>>>> its >>>>> too late for having a call today, but just wondering whether we can >>>>> have >>>>> a review tomorrow (Friday) if the draft version comes out today. >>>>> >>>>> >>>>> All, >>>>> I am hoping that we are fairly close to the final version, possibly >>>>> just >>>>> one more revision. I guess we have missed the deadline for DAC press >>>>> release as it requires one month period for Accellera review and >>>>> approval but at least hoping that we could announce at DAC that the >>>>> LRM2.3 has been frozen and sent for board approval. >>>>> >>>>> On this note, is anybody from this committee going to be at DAC? >>>>> Please >>>>> do send me a note on that. >>>>> >>>>> Regards, >>>>> Sri >>>>> -- >>>>> Srikanth Chandrasekaran >>>>> Design Technology (Tools Development) >>>>> Freescale Semiconductor Inc. >>>>> T:+91-120-439 5000 p:x3824 f: x5199 >>>>> >>>>> -- >>>>> This message has been scanned for viruses and >>>>> dangerous content by MailScanner, and is >>>>> believed to be clean. >>>> >>>> >>>> >>> >> > > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon May 12 08:27:12 2008
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