FW: FW: Verilog-AMS Committee Meeting - 12 May 2008 (Monday)

I received the following question from an engineer who is working on
implementing Verilog-AMS in a simulator.  Can someone on the committee
please answer his question?

Thanks,

Stu
~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland
stuart@sutherland-hdl.com
+1-503-692-0898

> -----Original Message-----
> From: Stephen Williams [mailto:steve@icarus.com]
> Sent: Monday, May 12, 2008 9:05 AM
> To: stuart@sutherland-hdl.com
> Subject: Re: FW: Verilog-AMS Committee Meeting - 12 May 2008 (Monday)
> 
> Can I ask you another quick question? I encountered this over the
> weekend. (a) Do natures need to be declared before they can be used
> in disciplines? (b) Do disciplines need to be declared before they
> can be used to declare analog nets? I think the answer is "yes"
> if I carefully read some of the wording, but I'm not sure. In the
> rest of Verilog, many things do not in general need to be declared
> before use so this would be a departure, but I'm finding that
> parsing net discipline declarations would be scary-hard without
> that restriction. In particular:
> 
> ~    IDENTIFIER list_of_identifiers ';'
> 
> is just asking for shift/reduce conflicts and is not practical,
> whereas:
> 
> ~    DISCIPLINE_IDENTIFIERS list_of_identifiers ';'
> 
> works nicely assuming the lexor gets into the act. This is what
> I've done, but it's not clear to me from the LRM (including drafts)
> that this is a legal constraint.
> 
> 
> - --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."


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