Re: FW: FW: Verilog-AMS Committee Meeting - 12 May 2008 (Monday)

Hi Steve,
yes in Verilog-AMS the type must be defined before it is referenced (similar to 
all/most procedural languages)

So you must define the nature before using it in a discipline.
You must define the discipline before declaring a node of that type.
A variable must be declared before it is used inside analog behaviour etc.

There are a couple of exceptions to this:
* You may instantiate a module before it is defined.
* You may reference an analog user defined function before it is defined.
* You may use an implicit net inside an instantiation. (implicit net is one 
that has not been explicitly declared). Note in Verilog-AMS, you are not 
allowed to access implicit nets inside analog behaviour, they can only be used 
in structural statements.
For example:
module top;
   // OK, a and b are implicit and can be used in structural stmts.
   resisitor #(.r(1)) r1(a,b);
endmodule

module top;
   // BAD, implicit nets a and b can't be used in behaviour.
   analog V(a,b) <+ I(a,b) * 1;
endmodule

I believe this may differ from Verilog where you can use implict nets inside 
behaviour.
module top
   // I think this is legal in digital.
   assign net = 1'b1;
endmodule

Hope this helps.
Cheers...
Dave


Stuart Sutherland wrote:
> I received the following question from an engineer who is working on
> implementing Verilog-AMS in a simulator.  Can someone on the committee
> please answer his question?
> 
> Thanks,
> 
> Stu
> ~~~~~~~~~~~~~~~~~~~~~~~~~
> Stuart Sutherland
> stuart@sutherland-hdl.com
> +1-503-692-0898
> 
>> -----Original Message-----
>> From: Stephen Williams [mailto:steve@icarus.com]
>> Sent: Monday, May 12, 2008 9:05 AM
>> To: stuart@sutherland-hdl.com
>> Subject: Re: FW: Verilog-AMS Committee Meeting - 12 May 2008 (Monday)
>>
>> Can I ask you another quick question? I encountered this over the
>> weekend. (a) Do natures need to be declared before they can be used
>> in disciplines? (b) Do disciplines need to be declared before they
>> can be used to declare analog nets? I think the answer is "yes"
>> if I carefully read some of the wording, but I'm not sure. In the
>> rest of Verilog, many things do not in general need to be declared
>> before use so this would be a departure, but I'm finding that
>> parsing net discipline declarations would be scary-hard without
>> that restriction. In particular:
>>
>> ~    IDENTIFIER list_of_identifiers ';'
>>
>> is just asking for shift/reduce conflicts and is not practical,
>> whereas:
>>
>> ~    DISCIPLINE_IDENTIFIERS list_of_identifiers ';'
>>
>> works nicely assuming the lexor gets into the act. This is what
>> I've done, but it's not clear to me from the LRM (including drafts)
>> that this is a legal constraint.
>>
>>
>> - --
>> Steve Williams                "The woods are lovely, dark and deep.
>> steve at icarus.com           But I have promises to keep,
>> http://www.icarus.com         and lines to code before I sleep,
>> http://www.picturel.com       And lines to code before I sleep."
> 
> 

-- 
=====================================
-- David Miller
-- Design Technology (Austin)
-- Freescale Semiconductor
-- Ph : 512 996-7377 Fax: x7755
=====================================

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.