Re: Minutes of the Verilog-AMS committee call: 12 May 2008

Geoffrey,

I just did a cut-paste of this from Section 7.3.2 of Draft4-Prelim which 
had this AnalogVar. I should have noticed it before sending, but looks 
like this has not been fixed to avar in that example - declaration and 
the analog begin-end. The rest of the example has it correctly as avar.

Regards,
Sri


Geoffrey.Coram wrote:
> Sri Chandra wrote:
>> * [clause 10.6, page 257]: Add an example for keywords that is no 
>> longer keyword in the current version.
>>
>> `begin_keywords "VAMS-2.3"
>> module a2d(dnet, anet);
>>   input dnet;
>>   wire dnet;
>>   logic dnet;
>>   output anet;
>>   electrical anet;
>>   real AnalogVar;
>>
>>   analog begin
>>     ...
>>   end
>> endmodule
>> `end_keywords
> 
> 
> Let's not repeat this error: it's "avar" not "AnalogVar"; we've
> had a few passes trying to clean up that example ...
> 

-- 
Srikanth Chandrasekaran
Design Technology (Tools Development)
Freescale Semiconductor Inc.
T:+91-120-439 5000 p:x3824 f: x5199

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