RE: FW: FW: Verilog-AMS Committee Meeting - 12 May 2008 (Monday)

From: Bresticker, Shalom <shalom.bresticker_at_.....>
Date: Tue May 13 2008 - 05:42:05 PDT
Not generally in behavioral constructs, only in continuous assignments.

Many people don't even consider continuous assignments to be behavioral
constructs.

Shalom
 

> I believe this may differ from Verilog where you can use 
> implict nets inside behaviour.
> module top
>    // I think this is legal in digital.
>    assign net = 1'b1;
> endmodule
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Received on Tue May 13 05:44:09 2008

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