Just a heads-up that stuff is going on at the p1801 committee that you might want to be aware of: http://www.eda-stds.org/p1801/hm/0383.html - Proposal for annotating attributes in Verilog, SystemVerilog, and VHDL http://www.eda.org/twiki/bin/view.cgi/P1801/WebHome Strikes me that this is another case of unnecessary EDA committee divergence. A chunk of the p1801 work should be getting handled directly by SV/AMS/VHDL language committees - e.g. attributes about power could be added into the AMS discipline mechanism, and would be useful to proper connect-module insertion. Kev. -- True Circuits Inc. - http://www.truecircuits.com Tel: (650) 949 3400 Ext 3415 -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon Aug 4 10:45:56 2008
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