Verilog-AMS LRM v2.3 approved

Hi all,

I got news from Accellera chair that the LRM v2.3 language standard has 
been approved by the Board.

Thank you all for your efforts for your valuable technical contributions 
and also with your valuable time (I understand the timezones don't suit 
lot of people in the call given the diverse locations we have got). I 
believe we have a very strong standard with LRM v2.3 with an unified 
mixed signal language definition and very key to move ahead on the next 
set of activities in terms of SV integration, AMS assertions and 
enhancements to the core AMS language itself.

Once again thank you all for your commitment in making this happen.

I need to create a new version with the "draft" removed from the version 
tag and the date changed to 4th August.

Regards,
Sri
-- 
Srikanth Chandrasekaran
Design Technology (Tools Development)
Freescale Semiconductor Inc.
T:+91-120-439 5000 p:x3824 f: x5199

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