Yes, this was discussed today and Dave is going to add a section in the next draft. cheers Geoffrey.Coram wrote: > Do we need a new section in Annex G, on the changes from previous LRMs? > > -Geoffrey > > > > David Miller wrote: >> http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/v2.3.1_drafts/VAMS-LRM-2-3-1-Draft-C.pdf >> >> >> The following was addressed: >> >>> #2581 - 3.12 - Last sentence in paragraph 3 should read: >>> >>> There shall be at most one unnamed branch between any two nets or >>> between a net >>> and implicit ground (in addition to any number of named branches). >>> >>> * 5.4.1 - Example 2 sub point 1. Last sentence should read: >>> >>> There can only be one unnamed branch between any two nets or between >>> a net and >>> implicit ground (in addition to any number of named branches). >>> >>> #2266 - D.1 - for the signal flow current it should be current >>> Current not >>> potential Current. >>> >>> # MISC - at the start of the grammar, add the sentence: >>> The following grammar is designed as a presentation grammar and >>> should not be >>> interpreted as an unambiguous production grammar. The compiler >>> developer will be >>> required to implement the various semantic restrictions outlined >>> through out >>> this reference manual to remove any ambiguities. >>> >>> # 2537 - Sub issue 7 - 6.4(.1)/A.1.9 - the >>> .module_parameter_identifier and >>> .system_parameter_identifier should be assigned a >>> paramset_constant_expression. >>> A paramset_constant_expression is a constant_expression minus the >>> reference to >>> parameters. The production should look like: >>> >>> paramset_constant_expression ::= constant_expression >>> | hierarchical_parameter_identifier >>> >>> >>> In 6.4.1 - the sentence should read: >>> The expression on the right-hand side can be composed of numbers , >>> parameters >>> and hierarchical out-of-module references to local parameters of a >>> different >>> module. Hierarchical out-of-module references to non-local parameters >>> of a >>> different module is disallowed. >>> >>> Also declare electrical gnd and replace reference to 0 with gnd in >>> example >>> 6.4.1 >> >> Issue 2497 /#13 analysis() function still needs to be addressed and I >> hope to have that done before the call tomorrow. >> >> Dave >> > -- Srikanth Chandrasekaran Design Technology Organization Freescale Semiconductor Inc. T:+91-120-439 5000 p:x3824 f: x5199 -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Feb 26 07:09:10 2009
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