I didn't see any reply to your query.
pmahe@avanticorp.com (Philippe Mahe) writes:
> We have an issue describing and backannotating single pin cells : example
> We have a bus holder :
>
> |\
> i _____| \o______
> | | / |
> | |/ |
> | /| |
> |____o/ |____|
> \ |
> \|
a>
> Pin I should be model wize an inout, so vital needs tipd_i statement.
> But in sysnopys we need to declare this as input because there is no function
> associated with this pin. Plus there is no timing for this cell.
Actually, it is not true to say that there is no functionality
associated with the pin, although synopsys may think that there is
not.
> The work arround we are using is to describe in synopsys the I pin as input,
> to have a vhdl model for the cell not a vital model.
How does this help you? In the VHDL model, if you are modelling the
bus holder functionality, you still need to declare I as an inout.
If you are truely not modelling the functionality, then simply make a
VITAL model with an input called I and no output. (I _think_ VITAL
will let you do this?).
If all else fails, complain to synopsys :-)
Martin.