HDL Synthesis & Simulation
Application Notes
XCell Articles
Other Links
to view the
PDF files below.
Application Notes
Title
Size
Design Files
Xilinx/Exemplar Large Device Design Methodology
400 KB
-
Xilinx/Synplicity High Density Methodology
140 KB
-
Synthesis and Simulation Design Guide
1.3 MB
Verilog
VHDL
Both
Source
WS
50 KB
50 KB
100 KB
PC
60 KB
60 KB
120 KB
Synopsys (XSI) Synthesis and Simulation Design Guide
1.3 MB
Verilog
VHDL
Both
Source
WS
50 KB
50 KB
100 KB
PC
60 KB
60 KB
120 KB
Source +
Implementation
WS
5 MB
6 MB
11 MB
PC
3 MB
4 MB
7 MB
XAPP108: Chip-Level HDL Simulation Using the Xilinx Alliance Series
200 KB
-
XAPP105: A CPLD VHDL Introduction
60 KB
-
XCell Articles
Title
Issue
Special XCell 29 Section: HDL Verification
Q3 '98
Synplify Extends Timing Constraint Control for Mixed Entry
Q3 '98
Looking for the Best HDL Design Flow?
Q3 '98
HDL Advisor: How to Use the Clock Enable Pin Instead of Gated Clocks in HDL Designs
Q3 '98
HDL State Machine Technique
Q3 '98
High-Level Design Tips for Synopsys FPGA Express
Q2 '98
Reduce Compile Times Using Timing Constraints in Foundation Express
Q2 '98
HDL Analyst - A Unique Tool for Visualizing Synthesis Results
Q2 '98
RAM Inference Using Exemplar Logic's Leonardo
Q2 '98
Synplify - Achieving Optimal Results
Q1 '98
New UNISIM Libraries for Functional VHDL and Verilog Simulations
Q1 '98
Foundation Series Software Now Delivers VHDL and Verilog
Q1 '98
HDL Synthesis and Built-In Clock Enables
Q2 '96
Synopsys Introduces FPGA Express
Q3 '96
Other Links
Xilinx Software Solutions
Xilinx Foundation: Superior Synthesis
Xilinx Alliance Partners
HDL Verification: We Will Take You to the Leaders
LogiBLOX Module Generator
Expert Journals
Synopsys FPGA Express
Synopsys FPGA Compiler
Foundation
Cadence
Mentor
Viewlogic
Customer Training