Answers Database

EZTAG: Basic debugging techniques for downloading design


Record #2939

Product Family:  Software

Product Line:  EPLD Core

Problem Title:
EZTAG:  Basic debugging techniques for downloading design


Problem Description:
Keywords:  9500, CPLD, EZTAG, Error 1017, chain,

Urgency:  Standard

General Description:  When having errors while trying to
download a design to a 9500, try the following steps to debug
the problem.  This solution is for using the EZTAG software
that was released with the Xact 6.0.1 tools, if you are using
the M1 tools, refer to (Xilinx Solution 3294).


Solution 1:

Be sure to have the latest patches installed.  They can
be found at ftp://ftp.xilinx.com/pub/swhelp/cpld.  The files
to use are CPLD.LST, FITTERPC.ZIP and EZTAG_PC.ZIP.  The
CPLD.LST is the main README file.  Read this file for
installation instructions and details as to what was patched.

These patches fix a variety of problems.  Mainly errors that
occur in Windows 95.  This is caused because the tools were
developed in Windows 3.x and not fully tested under Windows 95.
The patches fix errors 1017 (see (Xilinx Solution 1168),
resolution 3) and 'Can't find file "."'.

Also see (Xilinx Solution 1629) and (Xilinx Solution 1176)



Solution 2:

If you are using the JTAG cable (model DLC5) make sure there
is less than five devices in the chain, and only one device
in the chain if you are using the XCHECKER cable.  If you are
using more than the recommended number of devices you will need
to buffer the four JTAG signals.

Also see (Xilinx Solution 1272)



Solution 3:

If you are using the JTAG cable, make sure the serial number
is above 5000.	There are some known issues with parallel ports
and devices with numbers below 5000.

Also see (Xilinx Solution 1605)



Solution 4:

Check that there are decoupling CAPS attached to each VCCINT
and VCCIO pin, to nearest GND. Recommended capacitor values
are 0.1uF and 0.01uF.



Solution 5:

Check the supply voltage to the POD of the cable.  Make sure
that VCC is 5v and the GND is connected to a common ground with
the device that is being programmed.



Solution 6:

Check for noise on the board.  The TCK pin is very sensitive
and can cause problems when trying to configure.  Try putting a
small capacitor between TCK and GND.

Also, disable all free running clocks, if possible. Fast
clocks may introduce "extra" signals on to an otherwise quiet
chip.




Solution 7:

Check that the JTAG download cable is attached directly to
the parallel port on the PC.  Make sure there are no hardware
keys between the PC and the cable.



Solution 8:

If you are using the XChecker cable (Model DLC4), make sure you
have the RD pin on the cable connected to the TDO pin of the
CPLD.



End of Record #2939