| Product Feature |
Applications |
| Concept Unified Libraries |
-
Xilinx Unified schematic symbols for Concept design entry, i.e. xce3000,
xce4000e, xce4000ex, xce5200, xce7000, xce9000.
|
| Concept VAN-compiled Unified Libraries |
-
VAN-compiled libraries are used during concept2xil netlisting process.
xce3000_syn, xce4000e_syn, xce4000ex_syn, xce5200_syn, xce7000_syn, xce9000_syn
|
| Unified Verilog Simulation Libraries |
-
Enable Verilog functional simulation
|
| Concept Front-end Netlister: concept2xil |
-
Generate Verilog functional simulation netlist from Concept schematic design.
-
Translate Concept schematic design to EDIF 2 0 0 netlist for Xilinx M1
design implementation.
|
| Xilinx Back-end Verilog Netlister: NGD2VER |
-
Generate structural Verilog simulation netlist (*.v), SDF timing file (*.sdf)
and a Verilog simulation test fixture template. These files are read by
Cadence Verilog-XL simulator.
|
| Board-level Back-end Netlister: xil2cds |
-
Generate board-level simulation interface netlists: "chips_prt" and "body"
files.
|
| Cadence Interface User Guide and Tutorial |
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Design guide for Concept-Xilinx design implementation and a sample design
tutorial.
|
| Cadence XACTStep to M1.3 Design Conversion Guide |
-
Conversion guide for migrating existing Concept XACT design to Concept
M1 flow.
|
Overview