| Exemplar is a leading provider of FPGA Synthesis tools and Xilinx is
committed to providing the best Exemplar/Xilinx solution to its customers.
The matrix below shows support of Xilinx architectures in Galileo and Leonardo
tools
Both Galileo and Leonardo tools support the following general and Xilinx
specific features
-
Verilog and VHDL/VITAL
-
SDF Backannotation for Timing Analysis
-
Timing Analysis
-
Schematic Viewer
Both tools support the following Xilinx specific optimization features
-
Unified Library
-
Complex IO mapping
-
LUT Optimization
-
XC3K, XC4K, XC4KE, XC5K, XC4KXL based technologies
-
MODGEN support for operator generation
-
User Defined State Machine Encoding
-
Carry Chain synthesis support
-
CLB packing
-
GSR inferencing
Features specific to Galileo
-
Simple, non-interactive and encapsulated user interface
Features specific to Leonardo:
-
Support for clock, input delay, output delay, load and maxcap timing constraints
-
Full constraint based critical-path timing optimization
-
Hierarchical Database
-
Group and Ungroup hierarchy manipulation commands
-
TCL/TK scripting language
-
ASIC technologies
-
Interactive command line option
-
Design Hierarchy Browser
-
RAM inference from RTL and HDL
-
Counter inference from RTL and HDL
Specific Features in the new Release to support Xilinx Alliance Series
A1.3*
-
Support for M1 flow for both EDIF and XNF. EDIF netlist includes unified
library cells, XNF writes out Xilinx primitives. EDIF Flow includes writing
out FMAPS/HMAPS
-
Support for XC4000EX, XC4000XL and XC9500 technologies
-
Enhanced GSR support including GSR processing across hierarchy
-
Fast IO Buffers on XC4000 and XC5000 technologies slew rate is set fast
for all input and output buffers
-
Improved accuracy on delay estimates for the XC4000, XC4000E, XC4000EX,
XC4000XL and XC5000 technologies
-
Added CLB packing to the XC4000E and XC4000EX technologies
*Xilinx Alliance Series Design Environment
The Alliance Series represent Xilinx's next generation baseline technology
for implementation and integration functions. This advanced technology
enables digital system designers to increase design performance, leverages
standards-based, high-level design methodologies, and quickly receive future
software updates and device support for Xilinx FPGA and CPLD devices.
The Alliance Series technology provides dramatically improved design
performance through advanced placement and routing algorithms, powerful
"auto-interactive" design tools delivering the choice between a push-button
or manually-directed design flows, and support for standards based design
methodologies including EDIF, SDF, VHDL and Verilog. |
Overview