Xilinx Alliance Series - Product Details


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Products

Xilinx/Mentor Graphics Interface offers the best system level design solution for Programmable Logic market. The interface provides support of the latest version of Mentor Graphics software version B.4, mixed-level design entry solution with HDL, schematics and Cores. Direct Interface is available to Xilinx Place and Route tools via industry standard netlisting (EDIF 2.0.0), SDF for back annotating timing. Xilinx Alliance Series product generates standard Verilog and VHDL, which can be quickly verified in QuickHDL and QuickHDLPRO.

For high-density designs the solution provides the ability to instantiate high level macros in the schematics or HDL with the unique LogiBLOX solution from Xilinx. The designer calls up the LogiBLOX user interface directly from Mentor`s Design Architect, enters a list of parameters like bus width and the tool automatically generates a symbol and VHDL model for high level macros like adders and multipliers. This seamless integration cuts down on design time and results in dramatically reduced time to market.

Highlights

Support of latest version of Mentor software version B.4
Alliance Series compatible
Cross Probing of original schematics
Mixed level design entry and Verification support
Functional simulation support
LogiBLOX support
VHDL and Verilog solution with QuickHDL

Mentor Design Manager

The Mentor Graphics Design Manager is an easy-to-use interface that represents applications and design files as icons. The Designer can now perform tasks in the Design Manager window that were previously done at the operating system level. The Xilinx script, pld_dmgr, configures the Design Manager for creation, implementation, and simulation of Xilinx designs.

HDL Solution

The new solution provides support of QuickHDL simulator, which simulates behavioral VHDL, Verilog, VHDL-based and Verilog based gate level designs. In addition, LogiBLOX elements can be simulated at the behavioral level.

Support is also available for QuickHDLPRO for mixed mode simulations for schematic-based and VHDL-based designs. QuickHDLPRO can invoke QuickHDL to simulate VHDL VHDL-based elements. The new solution also supports gate-level simulation. Xilinx implementation tools output timing simulation VHDL and Verilog netlist.