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 Xilinx Synopsys Flow Overview

 
 		 Full screen view of Synopsys FPGA Express Implementation Flow Diagram printable in landscape mode. 

Text description of the Synopsys FPGA Express Implementation
 
 		 Full screen view of Synopsys FPGA Compiler Implementation Flow Diagram 

Text description of the Synopsys FPGA Compiler Implementation 
 
 		 Full screen view of Synopsys Design Compiler Implementation Flow Diagram  

Text description of the Synopsys Design Compiler Implementation
 

Training & Presentation Materials

Technical Information

Alliance Series 1.3 (Synopsys) Product Description

Product Feature Applications/Description/Availability FC DC FE
Synopsys Unified Libraries 
  • Xilinx Unified cells for instantiation into the HDL code.
 yes yes no
Unified VHDL/Verilog Simulation Libraries 
  • Enable VHDL or Verilog functional simulation. This capability will be available in Alliance Series 1.4.
 n/a n/a n/a
DC2NCF
  • Translates Synopsys timing constraints from the DC script into the NCF format.
 yes yes n/a
Xilinx Back-end VHDL Netlister: NGD2VHDL
  • Generate structural VHDL simulation netlist (*.vhd), SDF timing file (*.sdf) and a VHDL simulation test fixture template. These files are read by Synopsys VSS simulator. 
 n/a n/a n/a
XSI FPGA User Guide
  • Design guide for Synopsys-Xilinx design implementation and a sample design tutorial. 
  • HDL coding styles also apply to FPGA Express.
 yes yes yes
Synopsys HDL Synthesis for FPGA Design Guide 
(a.k.a. Xilinx HDL Synthesis for FPGAs Design Guide)
  • A new generic HDL Design Guide will be part of A1.4. This book will contain simulation flows and design methodologies.
  • HDL coding styles also apply to FPGA Express.
  • The availability of this book will be announced on this WEB page as soon as the date becomes available.
 yes yes yes
 
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