Text Description of Xilinx-Synplicity

Xilinx - Synplicity Information
Overview	Product Details	Customer Testimonials
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Device Architecture Support

FPGA      XC4000E/L
                XC4000X (EX/XL/XV)
                Spartan
                XC5200
                XC3X00A
CPLD      XC9500

Xilinx Recommended Settings

For details, go to www.xilinx.com and see
"Product" -> "Software Solutions".

Xilinx Contacts & Technical Support

World Wide Web: www.xilinx.com.

Phone: 1-800-255-7778 (NA), hotline@xilinx.com
Phone: 44 1932-820821 (UK), ukhelp@xilinx.com
Phone: 33 1-3463-0100 (France), frhelp@xilinx.com
Phone: 81 3-3297-9163 (Japan), jhotline@xilinx.com

HDL Library and Language Support

Synplify supports the synthesizable subsets of VHDL and Verilog HDL, including IEEE 1076-1993 and 1164 VHDL, and IEEE 1364-1995 Verilog HDL. For VHDL, Synplify supports the std library package called standard; the IEEE library packages std_logic_1164 and numeric_std; the Synplify library synplify and package attributes; the Synopsys std_logic_unsigned, std_logic_signed, std_logic_arith packages in the IEEE library; and user defined packages.

Synplicity Contacts & Technical Support

World Wide Web: www.synplicity.com

Phone: (408) 617-6000, support@synplicity.com

Synplify Flow Overview

1. Invoke Synplify.
This invokes the Synplify synthesis tool, and the Synplify Project Window is displayed listing Source Files, Result File, and Target information.

2. Specify your input files.
Press the ‘right’ mouse button in the Source Files list box, and select Add Source Files. Select Verilog or VHDL file(s) and click OK. (See the "synplcty \ examples" directory for examples.) You can also add files to the Project Window by dragging and dropping files from File Manager or Explorer.
Synplify picks the last module compiled as the top-level module for Verilog designs. For VHDL designs, Synplify picks the last architecture for the last entity in the last file compiled into Synplify.

3. Select your target architecture and options.
From the menu bar, choose Target -> Set Device Options… and choose your target architecture, and other options as desired and click OK.

4. Synthesize.
Synplify accepts timing constraints for synthesis and design constraints will be passed to the implementation tools. Please look at the Synplify On-line help for information on synthesis design constraints. Click the Run button. Synplify displays "Done!” when it completes successfully. Click the View Log button to view the Synplify Log File. Double click on the result file name if you wish to view the Synplify output file. You are now ready to place and route your design.

5. (Optional) Save this configuration in a Project File.

Synplify Recommended Settings: