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Xilinx-Synplicity Alliance Implementation Flow

  • Full screen view of implementation flow diagram printable in landscape mode. 
 

Xilinx Synplicity Alliance Series 1.4 Solution

Synplify 3.0b enhancements include the following Xilinx Quality of Results improvements: 
  • 11% smaller and significantly faster designs when optimizing the 4000 EX/XL family for area 
  • 2% faster and significantly smaller designs when  optimizing the 4000 EX/XL family for performance 
  • 4% smaller and 5% faster designs for the 5k family
  • More efficient multipliers and multiplexers
  • Added Critical Path Resynthesis for the XC5200 series
Powerpoint Presentation (last updated on 10/21/97)  Word Document (last updated on 10/21/97) 
 

Synplicity Product Feature Summary

Product Feature Applications
HDL Language Support
  • Verilog: IEEE 1364
  • VHDL: IEEE 1076, IEEE 1164, VHDL '93
  • VHDL library packages: IEEE std_logic_1164, numeric_std and Synopsys std_logic_unsigned, std_logic_signed, std_logic_arith
Synthesis Compile Times
  • Compile 100,000 gate designs in minutes
  • Run design iterations quickly to shorten design process
  • Fastest run time of all 3rd-party HDL synthesis tools
File Input
  • Verilog, VHDL, XNF
File Output
  • XNF output netlist
  • EDIF netlist (available in Alliance Series 1.4)
DST - Direct Synthesis Technology
  • Mapper will optimize efficiently to Xilinx architectures, i.e. CLB mapping - FMAPs, HMAPs usage, Xilinx M1 knowledgable 
Module Generation
  • Module generator for arithmetic operators (i.e. +, -), counters use built-in Xilinx carry logic cells (CY symbol)
  • Arithmetic functions are mapped directly to RPMs using the built-in carry logic, by passing LogiBLOX
  • Allows Synplify to map logic around the arithmetic function into the unused capacity of the lookup tables used for the arithmetic function
State Machines
  • Symbolic FSM Compiler automatically identifies and extracts state machines for optimization and re-encoding
IO Insertion
  • Option for automatic IO insertion
  • Instantiation of Xilinx-specific IO attributes, e.g. xc_nodelay, xc_fast, xc_slow
Global Set/Reset 
  • Option to insert Xilinx STARTUP module
TCL Script
  • Manually customized script to automate the Synplify synthesis option setting and run process
HDL Analyst
  • Instant schematic viewer for RTL and post-synthesis schematics 
  • Cross-probing between your RTL schematics, post-mapped schematics and HDL source code. 
 
 
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