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As a plug-in to the Simulink modeling software, the Xilinx System Generator provides a bit-accurate model of FPGA circuits, and automatically generates a synthesizable Hardware Description
Language (HDL) code and a testbench. This HDL design can then be synthesized for implementation in Xilinx Virtex® and Spartan®-II FPGAs. In a single source code you have an abstract representation of your system-level design which can be
easily transformed into a gate-level representation. Additionally, automatic generation of testbench enables design verification upon implementation.
To maximize predictability, density, and performance, the System Generator automatically maps the system design to Xilinx optimized LogiCORE modules. For more details on the Xilinx System
Generator for Simulink, please read the System Generator Design Flow Documentation.
You can significantly reduce development time by quickly iterating between a system representation and a hardware representation of your designs. This is especially important for DSP applications
because many system-level design tradeoffs are based upon the results of the hardware implementations. As a result, if you are new to FPGAs, you can use familiar tools from The MathWorks and Xilinx to apply FPGA technology to your DSP applications.
Xilinx Blockset
The Xilinx Blockset enables bit-true and cycle-true modeling, with Xilinx FPGA hardware as the target. It includes parametric blocks for DSP, arithmetic, and logic functions like FFTs, FIR
Filters, Multipliers, Memories, and gateway blocks to communicate with the MATLAB environment, where you also have access to the extensive set of Simulink libraries.
Each of the Xilinx blocks may be configured to many possible parameters and properties. Blocks are provided with a S-function for the Simulink representation and a synthesizable VHDL or LogiCOREs.
Special tokens are also made available to support user-defined black boxes and to invoke the System Generator interface to the Xilinx FPGA software. The Xilinx Blockset "Black Box" token
gives the ability to create specialized functions that may not exist in the current blockset and use them within the rest of the system.
System Generator Software
The Xilinx System Generator includes software to enable simulation, translation, and verification.
- The translation software is invoked from Simulink through the System Generator token and is used to generate VHDL code and cores for all the Xilinx Blockset elements on that sheet and on any sheets beneath it in its porject hierarchy.
FPGA designs are generated using Xilinx LogiCOREs, ensuring that the most efficient code is being generated.
- A VHDL testbench and data vectors can also be created for the generated design. These vectors represent the inputs and expected outputs seen in the Simulink simulation step and allow you to imediately notice any discrepancies between
the Simulink simulation and the VHDL simulation.
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