Tech Topics

What's New Overview: General Overview Virtex/Virtex-E           Virtex-EM Virtex-II Architecture Device Families: Virtex Virtex-E Virtex-EM                   Tech Topics  Datasheets  App Notes/Ref Designs  Configuration  Signal Integrity  Demo Boards Design Utilities: Chipscope ILA Power Estimator SelectLink Tool WebACE ZBT SRAM Calculator  More Information

5V-Tolerant I/Os To maintain technological leadership and continue to drive performance and logic density higher, chip manufacturers are constantly migrating to leading-edge fabrication processes. These processes continually decrease object geometry and consequently require lower core voltages to avoid damaging ever-smaller devices (3.3V, 2.5V, and 1.8V are widely used). Material pertains to all Virtex series devices unless specifically noted.   Technical details including the graphics and waveforms are available in PDF format.

While it is highly desirable to interface modern low-core-voltage devices with the older 5V devices that are still present on many customer boards, voltage and signaling differences frequently require the use of external voltage translator circuitry. The Virtex product family can interface directly with 5V systems without the need for translation circuitry. In fact, Virtex devices perform most efficiently in mixed-voltage systems. This tech topic addresses the interface of the Virtex and Virtex-E devices in mixed voltage systems.

In Virtex devices, all I/O standards have an intrinsic diode between the I/O pad and ground that limits undershoot to greater than -1V. The LVCMOS 2.5V, LVTTL, and PCI 5V standards are all 5V tolerant (both inputs and outputs) and do not have a pull-up clamp enabled. The PCI 3.3V (both 33 MHz and 66 MHz) and AGP standards have the pull-up clamp enabled but are not 5V tolerant, because the clamp itself limits the output to 4.4V maximum and sinks a significant amount of current when the pad voltage is raised above 4.4V.

Enhancements to the I/O structure of Virtex-E devices minimize pin capacitance and maximize performance. These differences, while conferring clear performance benefits for Virtex-E customers, also make the 5V-interface capability much more challenging.

Virtex-E devices are provided with a pull-up clamp diode between the I/O pad and VCCO, which allows them to be 5V tolerant and reduces overshoot. The clamp diode is available with all I/O standards excluding LVDS, LVPECL, GTL, GTL+, or LVCMOS1.8/2.5. To make the Virtex-E LVCMOS I/Os receive and drive 5V signals, an external clamp diode must be provided. In Virtex-E devices , all I/O standards have an intrinsic diode between the I/O pad and ground that limits undershoot to greater than -1V.

5V I/O Tolerance Definition

5V input tolerance is defined as the ability to connect an ideal 5.5V voltage source (assuming +/- 10% power supply tolerance) to the input pin of a device without damage. 5V-output tolerance is a little more complex, because there are two dominant 5V signaling standards: TTL and 5V CMOS.

Virtex and Virtex-E devices can each drive a 5V TTL input signal. Virtex-E devices cannot directly drive out 5V CMOS levels, because they cannot drive 5V CMOS VIH levels. Table 1 summarizes the Virtex and Virtex-E capabilities as drivers of 5V compatible signals.

Table 1. Virtex Series FPGA 5V I/O Support Summary

Using a Virtex Device to Drive 5V CMOS-Level Signals

To drive 5V CMOS-level inputs, a pull-up resistor must be applied to the 5V Virtex output. Prior to driving a logic 1 data signal, the Virtex output must be tri-stated. This ensures no overlap or crowbar current in the input buffers of the 5V-receiving device.

The required Virtex output pin configuration is commonly called "open collector" or, more correctly, "open drain". This function is easily generated inside the chip by driving the data together with the active low Output Enable signal of the output block. The external low-to-high transition is then driven only by the pull-up resistor. For example, applying a 470-ohm pull-up resistor to 5V and a 50-pF load capacitance create a 0.4 to 4.5V rise time of about 40ns. Click here to view figure 1.

For a faster rise time, the internal active low Output Enable signal is not driven directly from the internal data signal. Instead, it is driven from a two-input AND gate that is driven by both the internal data signal and the input signal returned from the same device's output pin. On the rising edge, this assures that the output pull-up transistor is active for most of the rise time, resulting in a shorter output delay. The important part of the rise time from 0.4 to 3.0 V is reduced dramatically, from 20ns to 3ns. Click here to view figure 2.

Ringing can be avoided by following proper board design practices. In most cases, the fast active edge enables the CMOS threshold to be passed with a propagation delay of less than 3ns. At worst, an additional pullup from the resistor is still needed to reach the threshold voltage reliably, but this enables at least 15ns to be saved.

Using a Virtex-E Device as a Receiver of a 5V TTL Signal

The internal clamp diode to VCCO that is provided in Virtex-E devices with certain I/O standards, clamps the driving output to VCCO + VDiode (approximately 4.4V). This results in a large current sunk in the diode. By inserting a series resistor, the current is limited to some reasonable value, for example 10 mA. An internal diode can clamp the I/O pad to the value of VCCO + VDiode. Including the series resistor minimizes the current sink created by the clamp. For example, the 100-ohm resistance value is applied to the Virtex-E inputs to ensure that Virtex-E device meets all specification for the LVTTL I/O standard. The 100-ohm resistance value needed on the Virtex-E inputs is calculated using the following formula:

R = (5V - VDiode - VCCO) / 10mA

Assumptions used to obtain the resistor values are as follows:

• Maximum current limit is 10mA.
• VDiode is approximately 0.8V.

Note that applying a continuous voltage higher than 4.4V to the Virtex-E inputs that do not have a diode to VCCO (for example; GCLK, MODE, and JTAG pins) is not allowed and damages the inputs. Although the damage might not be instantaneous, the long-term reliability of the design can be impacted.

A 5V device can drive a standard Virtex-E I/O pin (excluding GCLK, MODE, and JTAG pins), provided the following conditions are met:

• The Virtex-E pin is input only.
• The IBUF is configured to have a clamp to VCCO (This is not possible with LVDS, LVPECL, GTL, GTL+, or LVCMOS1.8/2.5 I/Os).
• A current-limiting resistor (100 ohms) is placed in series with the pad.
• VCCOMAX is 3.6V and VPADMAX is 4.4V. The Virtex-E device must never discharge a pad driver from a voltage higher than 3.6V. However, occasional ringing, which might cause the pad to rise above 3.6V momentarily, is not a problem.

Provided the above conditions are met, damage to Virtex-E devices can be avoided.

Possible Solutions for Clamping the Voltage to 3.6V

Solution 1: External Resistor Clamp Circuit
An external resistor divider circuit could be provided; however, the sizing of these resistors must be based on the IOH and IOL values specified for the 5V device. The IOH and IOL values are specified at VOH and VOL and are specified as worst-case low current, respectively. Since resistor clamps result in a voltage that is different from VOL/VOH, and drive current might exceed tested minimum values, drive current is likely to differ from the data sheet specification. The difference in the drive current makes this solution more difficult to implement.

Solution 2: External Active Clamp Circuit
Another solution that eliminates the need for external resistors is to have active clamp circuitry. Click here to view figure 3 which shows a diode stack that limits the pad voltage to 3.6V or less.

Virtex-E as a Driver of a 5V TTL Device

A Virtex-E part can drive an input-only signal on a 5V TTL device, provided that the 5V TTL VIL and VIH requirements are met. As long as no path to 5V exists at the driven device's pad, this solution works.

Virtex-E devices are not 5V PCI-compliant; however, a Virtex-E input-only signal can be driven by a 5V PCI part in a PCI system, provided that all of the requirements mentioned in Note 3 (see Table 1) are met. The effect of having a Virtex-E input-only signal on a PCI bus is to limit the maximum logic high value on that bus to VCCO (for Virtex-E devices) + VDiode. Another effect is the increased delay to the Virtex-E input-only pin, due to the current-limiting resistor. The current-limiting resistor can change the impedance of the bus, thereby impacting signal integrity.

Virtex Advantages

Virtex series FPGAs are capable of providing 5V-compatible I/Os. The original 2.5V Virtex family provided a direct interface to external 5V devices without any external glue logic/components, and the Virtex-E family can also interface with 5V devices when proper serial resistors or clamping circuitry are applied.

Neither APEX nor APEX E 20K devices are 5V tolerant. The APEX devices also have no recommendations for external clamping circuitry, since these devices are not characterized for 5V tolerance. This could be due to the fact that degenerative failure can occur to the transistors in their I/O cells. For these reasons, the Virtex series FPGAs are the ideal solution when designing high-performance systems with mixed voltage devices.

References

Related Xilinx Documents
to view the  PDF files below.

Related Xilinx Documents/Ref. Designs Version File Size Date Using the Virtex SelectI/OTM Resource 2.2 229K 2/22/00 5V-Tolerant I/Os NA 32K 3/27/00

More Information  Virtex Overview Wireless Connection Memory Corner System Timing   System Interface  System Design

Product Information    Software    IP Center    Hard Copy Literature Request