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Tech Topics
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Xilinx Fine-Pitch BGA and CSP Packages : The Technological Edge
Rapid evolution of complex electronic systems and the demand for improved functionality at lower cost have resulted in the need for silicon products with smaller footprints. Advanced packaging options for the Virtex Series of FPGAs,
such as the widely offered Xilinx fine-pitch Ball Grid Arrays (FG), have a tighter, 1.00-mm pitch versus the 1.5-mm and 1.27-mm pitches of conventional Ball Grid Arrays (BGAs). Xilinx is the first company in programmable silicon market
to offer Chip Scale Packages (CSP) with a 0.8-mm pitch. This small form factor packaging solution has been used successfully with Xilinx XC9500 series CPLD products up to 100,000 system gates and is being implemented for the Virtex
Series FPGAs up to 200,000 system gates.
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Material pertains to all Virtex series devices unless specifically noted.
Technical details including the graphics and waveforms, are available in PDF format.
Xilinx Fine-Pitch BGA and CSP Advantages
A significant advantage of using fine-pitch BGAs and CSPs is the dramatic reduction in printed circuit board (PCB) real estate with an increase in I/O counts. Fine-pitch BGAs and CSPs are ideally suited for space-sensitive applications that
provide package area reductions greater than 50% compared to traditional BGAs. Those packages also increase the I/O count support (over 200%) in the same real estate compared to the previous generation of BGAs. Table 1 compares various features
of the three package types discussed.
Feature/Package
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BGA
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FG
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CSP
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Pin Count
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256
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256
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280
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Lead Pitch
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1.27-mm
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1.0-mm
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0.8-mm
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Package Dimension
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27 x 27
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17 x 17
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16 x 16
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Lead Count
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1x
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1x
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1.1x
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Package Area
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1x
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.4x
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.35x
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Table 1: BGA/ Fine-Pitch BGA/ CSP Features Comparison
Additional Critical Package Features and Advantages
Xilinx fine-pitch BGAs are available in 256, 456, 676, 680, 860, 900, and 1156 solder ball arrays.
- The Xilinx fine-pitch BGA packages are based on the original Motorola BGA technology, which has a well-established worldwide supply base and infrastructure that ensures abundant substrate and assembly sources. These packages have a lower
overall cost structure as well as the potential for rapid cost reductions in the future due to multiple sourcing.
- Board-level reliability of Xilinx fine-pitch BGA packages is far superior to that of Flex-based (polymide tape with one or two metal layers) packages for similar applications. Although Flex-based products have a smaller form factor, the
package mechanical reliability is usually dominated by the die properties. Reliability worsens as the ball array is fully populated and the die size increases. For Flex-based packages, the coefficient of thermal expansion (CTE) mismatch
between the package and the board is larger, resulting in a less reliable product than the Xilinx fine-pitch BGA solution.
- Table 2 illustrates the board-level reliability of fine-pitch BGAs compared to that of Flex-based packages of similar size. The data was gathered using the temperature range of -40 to +125°C. Almost all (~98%) of the 484-pin Flex-based
packages (23 mm x 23 mm) failed after 800 cycles of 1 cycles per hour thermal cycling condition. The 676-pin fine-pitch BGAs from Xilinx, although larger in dimension (27 mm x 27 mm) than the 484-pin Flex-based BGAs, did not show any failure
until 1350 cycles passed under the same conditions. This clearly indicates superior board-level performance of Xilinx fine-pitch BGA packages over Flex-based package alternatives adopted by other FPGA vendor.
Package Type (mm x mm)
(1.00 mm ball pitch)
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Number of Cycles at Which 10% of the
Sample Population Failed
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Number of Cycles at Which 98% of the Sample Population Failed
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484-Pin Flex BGA (22x22)
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500
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800
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676-Pin Fine-Pitch BGA (27x27)
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1500
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2000
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Table 2:System Reliability Comparison Between Flex-Based BGA And
Xilinx Fine-Pitch BGA Packages
Diagram 1: Thermal Resistance comparison between Xilinx FG products and Flex-based products
- Diagram 1 compares package thermal resistance data at different air flow rates for Flex-based packages and Xilinx fine-pitch BGA packages. Clearly, the fine-pitch BGA solution from Xilinx has lower thermal resistance than the Flex-based
alternatives, which translates to better thermal performance and higher reliability.
- The fine-pitch BGA solution is capable of accommodating high performance future Xilinx products, especially in the Flip Chip format, with minimal changes in mechanical features. This package technology will provide a smoother transition
to high performance, high I/O solutions for our customer base, whereas Flex-based solutions are limited in their capacity to accommodate the additional I/O of future products.
Xilinx CSP/Fine-Pitch BGA Strategy
CSP
Xilinx has chosen the Flex-based technology for low pin count CSPs. Flex-based packages enable die shrink migration while providing the lower-profile advantages for low pin count packages. Xilinx is the first company in the programmable
logic industry to provide CSP packages for FPGAs and CPLDs that meet JEDEC Level-3 Moisture Resistance specification.
Fine-Pitch BGA Pin Array Compatibility
Xilinx provides flexibility by supplying Pin Array Compatibility (PAC) between the FG456 and FG676 packages. The PAC feature provides system designers the flexibility to lay out one printed circuit board (PCB) for these two fine-pitch BGA
packages. Diagram 2 demonstrates the compatibility of the two fine-pitch BGA packages.
Diagram 2: Fine-Pitch BGA Pin Array Compatibility
Xilinx Fine-Pitch BGA PCB Routability Advantage
The industry has recently started to adopt fine-pitch BGAs as a mainstream packaging technology. For users, 1.00-mm pitch packages can present both routing and silicon mount technology process challenges. Xilinx fine-pitch BGAs
solve these challenges and present a definite advantage over the Flex-based packages. Diagram 3 compares the I/O layout of a FG676 fine-pitch BGA package and a Flex-based package option. The fine-pitch BGA package is offered with I/Os that
are 8 rows deep. This enables customers to use standard 6-mil trace/6-mil spacing manufacturing technology. Comparable Flex-based BGAs have I/Os that are 10-11 rows deep resulting in problems accessing all the pins using the standard board
manufacturing technology.
![](../images/216fpvsfb.gif)
Diagram 3: I/O Layout Comparison of Xilinx Fine-Pitch BGA and Flex-based BGA Packages
The result is more expensive 4-mil lines/trace technology, often with microvias or additional PCB layers for routing, (see Diagram 4). This more complex manufacturing leads to higher system costs and lower reliability for customers
using large Flex-based packages.
![](../images/222fpvsfb.gif)
Diagram 4: PCB Routing Comparison of Xilinx FG and Comparable Flex-Based BGA Package
Mechanical samples with daisychained dies are available from Xilinx for evaluation purposes. Contact your local sales representative for details on ordering parts with package codes starting with FG (pin count)(daisychained).
Xilinx Fine-Pitch BGA and CSP Support
Table 3 summarizes the fine-pitch BGAs and CSP offerings available for the Virtex series Spartan series, and CPLD products.
Package Type
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Ball Count
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Package Size
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Max I/O
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Height
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Package Technology
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144
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12x12 mm
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94
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1.10 mm
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Flex-based CSP
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280
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16x16 mm
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196
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1.20 mm
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Flex-based CSP (Spartan™, CPLD)
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Fine Pitch
(1.00 mm)
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256
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17x17 mm
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176
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2.30 mm
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Plastic Molded BGA
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456
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23x23 mm
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312
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2.30 mm
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Plastic Molded BGA
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676
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27x27 mm
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444
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2.30 mm
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Plastic Molded BGA
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680
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40x40 mm
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512
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1.38 mm
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Cu-Based "SBGA"
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860
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42.5x42.5 mm
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660
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2.30 mm
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Cu-Based "SBGA"
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900
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31x31 mm
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700
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2.30 mm
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Plastic Molded BGA
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1156
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35x35 mm
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804
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2.30 mm
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Plastic Molded BGA
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Table 3: Xilinx CSP and Fine-Pitch BGA Offering
Virtex and Virtex-E FPGAs, ranging in density from 50,000 to 3,200,000 system gates are the first FPGAs to fully support these advanced packaging options. The 144-ball CSP package option is provided for devices in the 50,000
and 200,000 gates densities, while the FG package option is provided for all devices in the family. The FG offering includes the FG256, FG456, FG680, FG860, FG900, and FG1156 packages.
To maximize system design flexibility, the Virtex series provides multiple device densities within a given fine-pitch BGA package. This vertical migration capability enables designers to lay out their boards prior to finalizing
the FPGA design, thus gaining time-to-market advantages. Table 4 illustrates the footprint compatibility of the Virtex series.
Product |
XCV50
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XCV100
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XCV150
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XCV200
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XCV300
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XCV400
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XCV600
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XCV800
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XCV1000
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Package |
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CS144(12mmx12mm) |
I/O |
94
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94
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TQ144(20mmx20mm) |
I/O |
98
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98
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PQ240/HQ240(32mmx32mm) |
I/O |
166
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166
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166
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166
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166
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166
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166
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166
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BG256(27mmx27mm) |
I/O |
180
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180
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180
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180
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BG352(35mmx35mm) |
I/O |
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260
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260
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260
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BG432(40mmx40mm) |
I/O |
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316
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316
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316
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316
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BG560(42.5mmx42.5mm) |
I/O |
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404
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404
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404
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404
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FG256(17mmx17mm) |
I/O |
176
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176
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176
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176
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FG456(23mmx23mm) |
I/O |
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260
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284
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312
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FG676(27mmx27mm) |
I/O |
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404
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444
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444
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FG680(40mmx40mm) |
I/O |
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512
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512
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512
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Product |
XCV50E
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XCV100E
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XCV200E
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XCV300E
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XCV400E
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XCV600E
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Package |
Differential Pairs
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![](../images/shim.gif) |
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![](../images/shim.gif) |
![](../images/shim.gif) |
![](../images/shim.gif) |
![](../images/shim.gif) |
![](../images/shim.gif) |
CS144(12mmx12mm) |
30
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I/O
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94
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94
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94
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PQ240/HQ240(32mmx32mm) |
64
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I/O
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158
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158
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158
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158
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158
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158
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BG352(35mmx35mm) |
87
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I/O
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196
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260
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260
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BG432(40mmx40mm) |
137
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I/O
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316
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316
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316
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BG560(42.5mmx42.5mm) |
183
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I/O
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FG256(17mmx17mm) |
83
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I/O
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176
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176
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176
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176
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FG456(23mmx23mm) |
119
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I/O
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284
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312
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FG676(27mmx27mm) |
183
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I/O
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404
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444
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FG680(40mmx40mm) |
247
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I/O
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512
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FG860(42.5mmx42.5mm) |
281
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I/O
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FG900(31mmx31mm) |
260
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I/O
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512
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FG1156(35mmx35mm) |
344
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I/O
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Product |
XCV1000E
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XCV1600E
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XCV2000E
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XCV2600E
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XCV3200E
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Package |
Differential Pairs
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![](../images/shim.gif) |
![](../images/shim.gif) |
![](../images/shim.gif) |
![](../images/shim.gif) ![](../images/shim.gif) |
![](../images/shim.gif) |
CS144(12mmx12mm) |
30
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I/O |
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PQ240/HQ240(32mmx32mm) |
64
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I/O |
158
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BG352(35mmx35mm) |
87
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I/O
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BG432(40mmx40mm) |
137
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I/O |
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BG560(42.5mmx42.5mm) |
183
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I/O |
404
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404
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404
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FG256(17mmx17mm) |
83
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I/O |
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FG456(23mmx23mm) |
119
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I/O |
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FG676(27mmx27mm) |
183
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I/O |
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FG680(40mmx40mm) |
247
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I/O |
512
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512
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512
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FG860(42.5mmx42.5mm) |
281
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I/O |
660
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660
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660
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FG900(31mmx31mm) |
260
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I/O |
660
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724
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FG1156(35mmx35mm) |
344
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I/O |
660
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724
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804
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804
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CG1156(35mmx35mm) |
344
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I/O |
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804
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Table 4. Virtex Series Package Offering Summary
Virtex Advantages Summary
Xilinx packaging leadership addresses the industry demand for reduction in both system costs and size for portable systems. Xilinx offers 0.8-mm pitch CSP and 1.00-mm fine-pitch BGA packages that dramatically reduce board real
estate and increase I/O counts for the Virtex series of FPGAs.
Designed with proven mainstream manufacturing flows optimized to handle these low-pitch packages, Xilinx CSPs and fine-pitch BGAs are capable of providing the following advantages for our customers:
- Meeting Moisture level 3 spec, thus enabling customers to maintain standard manufacturing flow/cycle time
- Lower thermal resistance data, translating to better thermal performance and eliminating cost for additional board-level cooling component (ex. Fan)
- Better board level reliability as indicated in the thermal cycle analysis in table 2, providing higher system reliability and reduce cost for any rework required
- Pin-out compatibility across the Virtex series family, enabling customers to utilize the lowest cost package/device combination once the design in finalized
- Better routability, allowing customers to reduce overall system cost by reducing the layers of board needed and utilizing the standard board manufacturing technology
Combining the above mentioned advantages of the Xilinx leading-edge CSP and FG packaging with the high-performance Virtex system-level feature set, makes the Virtex series FPGA the ideal solution to create the reliable system design for
your next generation high-performance system.
References
Related Xilinx Documents
to view the
PDF files below.
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