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Tech
Topics
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High Speed Transceiver
Logic (HSTL)
Virtex Series of FPGAs feature the Xilinx exclusive SelectI/O+
technology integrating support for 20 single-ended and differential
I/O standards. HSTL is one of the single-ended I/O interfaces
supported by every Virtex device, eliminating the need for external
level translators to interface with high-speed memories and
reducing overall system design complexity and cost. Virtex FPGAs
are the only PLD solutions with integrated HSTL I/Os for memory
intensive designs.
Material pertains to
all Virtex series devices unless specifically noted.
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For more technical details including the graphics and waveforms, click
here to download the PDF version.
The HSTL Standard
HSTL is a technology-independent interface standard for digital integrated
circuits. It was developed for voltage scalable and technology independent
I/O structures. The I/O structures required by this standard are; differential
amplifier inputs (with one input internally tied to a user-supplied input
reference voltage for single ended inputs), and outputs using output power
supply inputs (Vcco) that may differ from those operating the device itself.
Advantages
- HSTL compliance does not specify device supply voltages, making it
a process-independent I/O standard. The lower voltage-level swing associated
with this standard makes high-speed HSTL I/O solutions possible for
any core voltage level device.
- A given circuit need not have all four classes of output drivers,
but each circuit must have at least one of the four classes to claim
HSTL output compliance.
- The HSTL nominal logic switching range is 0.0 V to 1.5 V, resulting
in faster outputs with reduced power dissipation, and minimized EMI
concerns.
- HSTL gives system designers enhanced flexibility in optimizing system
performance with adjustable trip-point (Vref) and output power supply
voltage (Vcco).
Applications
In computing, slow memory access times have traditionally hindered fast
processor operations. In the mid-frequency range (between 100 MHz and
180 MHz), the I/O interface options for all single ended signals are;
HSTL, GTL/GTL+, SSTL, and LVTTL. Beyond 180 MHz, the HSTL standard is
the only single ended I/O interface available. With HSTL speeds, faster
I/O interface significantly improves overall system performance. HSTL
is the I/O interface of choice for high-speed memory applications, and
are ideal for driving address buses to multiple memory banks.
Terminated Loads
The HSTL I/O standard specifies the output characteristics for both
series (Class II) and parallel (Class I, III, and IV) terminated loads.
The limiting factors in high-speed digital I/O circuits are the typical
transmission line effects (ringing, reflections, crosstalk, and EMI).
Transmission line reflections are the greatest constraint. Controlling
reflection requires impedance matching using parallel or series terminations.
There are four classes of HSTL output specifications depending on output
drive requirements. Virtex devices support all the push-pull output buffers
for parallel terminated loads (Class I, III, and IV.)
HSTL Class I Output Buffers
HSTL Class 1 output buffers have two types of loads:
- Push-pull output buffers for unterminated loads.
- Push-pull output buffers for symmetrically parallel terminated loads
(VTT = VCCO/2).
Click here to view the HSTL Class
I Output Buffer figure (PDF file).
Parameter |
Min |
Typ |
Max |
VCCO |
1.40 |
1.50 |
1.60 |
VREF |
0.68 |
0.75 |
0.90 |
VTT |
|
VCCO x 0.5 |
|
VIH |
VREF + 0.1 |
|
|
VIL |
|
|
VREF - 0.1 |
VOH |
VCCO - 0.4 |
|
|
VOL |
|
|
0.4 |
IOH at VOH
(mA) |
-8 |
- |
- |
IOL at VOL(mA) |
8 |
- |
- |
Table 1: HSTL Class I Voltage Specification |
It is not recommended to use the output buffers for unterminated loads
because of signal integrity issues, specifically ringing, affecting overall
performance by slowing down the outputs.
HSTL Class III Output Buffers
Push-pull output buffers for asymmetrically parallel terminated loads
(VTT = Vcco).
Click here to view the HSTL Class
III Output Buffer figure (PDF file).
Parameter |
Min |
Typ |
Max |
VCCO |
1.40 |
1.50 |
1.60 |
VREF(1) |
|
0.90 |
|
VTT |
|
VCCO |
|
VIH |
VREF + 0.1 |
|
|
VIL |
|
|
VREF - 0.1 |
VOH |
VCCO - 0.4 |
|
|
VOL |
|
|
0.4 |
IOH at VOH
(mA) |
-8 |
- |
- |
IOL at VOL(mA) |
24 |
- |
- |
1. Per EIA/JESD8-6, "The value of VREF is to be
selected by the user to provide optimum noise margin in the use conditions
specified by the user.
Table 2: HSTL Class III Voltage Specification |
HSTL Class IV Output Buffers
Push-pull output buffers for asymmetrically double parallel terminated
loads (VTT = VCCO).
Click here to view the HSTL Class
IV Output Buffer figure (PDF file).
Parameter |
Min |
Typ |
Max |
VCCO |
1.40 |
1.50 |
1.60 |
VREF(1) |
|
0.90 |
|
VTT |
|
VCCO |
|
VIH |
VREF + 0.1 |
|
|
VIL |
|
|
VREF - 0.1 |
VOH |
VCCO - 0.4 |
|
|
VOL |
|
|
0.4 |
IOH at VOH
(mA) |
-8 |
- |
- |
IOL at VOL(mA) |
48 |
- |
- |
1. Per EIA/JESD8-6, "The value of VREF is to be selected
by the user to provide optimum noise margin in the use conditions specified
by the user.
Table 3: HSTL Class IV Voltage Specification |
Virtex HSTL I/Os
The Virtex series HSTL I/O produces a substantial output swing from a
very small input swing. For all Virtex Class I, III, and IV I/Os:
- Customers may use IBIS models to compute the source impedance values
for their specific designs.
- Slew-rate control is not provided for the HSTL I/Os.
Click here to view the HSTL receiver/transmitter
figures and waveform (PDF file).
Virtex Advantages
Using the Xilinx exclusive SelectI/O+ technology, the Virtex series
delivers up to 804 single ended I/Os capable of supporting the HSTL standard
listed in Table 4. With every I/O capable of supporting this array of
I/O standards, the Virtex series of FPGAs provides maximum board layout
flexibility. By reducing overall system design complexity and cost, the
SelectI/O+ technology makes the Virtex series the ideal solution for direct
interfacing to high performance memory devices. Virtex devices are the
only FPGAs to support the HSTL I/O standard to seamlessly interface with
other high performance HSTL standard devices.
Supported Standards
Standard |
Virtex |
Virtex-E |
HSTL-I |
Yes
|
Yes
|
HSTL-II |
No
|
No
|
HSTL-III |
Yes
|
Yes
|
HSTL-IV |
Yes
|
Yes
|
Table 4. HSTL Support in Virtex Series |
References
Standard
EIA/JEDEC STANDARD EIA/JESD8-6
Related Xilinx Documents
to view the
PDF files below.
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