Create generated clock

Families Supported

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

Families

SDC

Timer/SmartTime

Fusion

X

X

ProASIC3E

X

X

ProASIC3

X

X

ProASIC PLUS

X

X

Axcelerator

X

X

ProASIC

X*

X*

eX

X

X

SX-A

X

X

SX

 

 

MX

 

 

3200DX

 

 

ACT3

 

 

ACT2/1200XL

 

 

ACT1

 

 

(*) Supported for analysis only

Purpose

Use this constraint to create an internally generated clock constraint, such as clock dividers and PLL. The generated clock is defined in terms of multiplication and/or division factors with respect to a reference clock pin. When the reference clock pin changes, the generated clock is updated automatically.

Tools /How to Enter

You can use one or more of the following methods to enter clock constraints:

See Also

Constraint entry

create_generated_clock (SDC)

Specifying generated clock constraint