create_generated_clock (SDC)

Creates an internally generated clock and defines its characteristics.

create_generated_clock -source reference_pin [-divide_by divide_factor] [-multiply_by multiply_factor] [-invert] source

Arguments

-source reference_pin

Specifies the reference pin in the design from which the clock waveform is to be derived.

-divide_by divide_factor

Specifies the frequency division factor. For instance if the divide_factor is equal to 2, the generated clock period is twice the reference clock period.

-multiply_by multiply_factor

Specifies the frequency multiplication factor. For instance if the multiply_factor is equal to 2, the generated clock period is half the reference clock period.

-invert

Specifies that the generated clock waveform is inverted with respect to the reference clock.

source

Specifies the source of the clock constraint on internal pins of the design. If you specify a clock constraint on a pin that already has a clock, the new clock replaces the existing clock. Only one source is accepted. Wildcards are accepted as long as the resolution shows one pin.

Supported Families

Fusion, ProASIC3/E, ProASICPLUS, Axcelerator, ProASIC (for analysis), eX, SX-A

Description

Creates a generated clock in the current design at a declared source by defining its frequency with respect to the frequency at the reference pin. The static timing analysis tool uses this information to compute and propagate its waveform across the clock network to the clock pins of all sequential elements driven by this source.

The generated clock information is also used to compute the slacks in the specified clock domain that drive optimization tools such as place-and-route.

Exceptions

None

Examples

The following example creates a generated clock on pin U1/reg1:Q with a period twice as long as the period at the reference port CLK

create_generated_clock –divide_by 2 –source [get_ports {CLK}] U1/reg1:Q

The following example creates a generated clock at the primary output of myPLL with a period ¾ of the period at the reference pin clk

create_generated_clock –divide_by 3 –multiply_by 4 -source clk [get_pins {myPLL:CLK1}]

Actel Implementation Specifics

SDC accepts either –multiply_by or –divide_by option. In Actel design implementation, both are accepted to accurately model the PLL behavior.
SDC accepts defining a generated clock on many sources using a single command. In Actel design implementation, only one source is accepted.
The -duty_cycle ,-edges and –edge_shift options in the SDC create_generated_clock command are not supported in Actel design implementation.