Design constraints are usually either requirements or properties in your design. You use constraints to ensure that your design meets its performance goals and pin assignment requirements.
The Designer software supports both timing and physical constraints. In addition, it supports netlist optimization constraints. You can set constraints by either using Actel's interactive tools or by importing constraint files directly into your design session.
Timing constraints represent the performance goals for your designs. Designer software uses timing constraints to guide the timing-driven optimization tools in order to meet these goals.
You can set timing constraints either globally or to a specific set of paths in your design.
You can apply timing constraints to:
Specify the required minimum speed of a clock domain
Set the input and output port timing information
Define the maximum delay for a specific path
Identify paths that are considered false and excluded from the analysis
Identify paths that require more than one clock cycle to propagate the data
Provide the external load at a specific port
To get the most effective results from the Designer software, you need to set the timing constraints close to your design goals. Sometimes slightly tightening the timing constraint helps the optimization process to meet the original specifications.
Designer software enables you to specify the physical constraints to define the size, shape, utilization, and pin/pad placement of a design. You can specify these constraints based on the utilization, aspect ratio, and dimensions of the die. The pin/pad placement depends on the external physical environment of the design, such as the placement of the device on the board.
There are three types of physical constraints:
I/O assignments
- Set location, attributes, and technologies for I/O ports
- Specify special assignments, such as VREF pins and I/O banks
Location and region assignments
- Set the location of Core, RAM, and FIFO macros
- Create regions for I/O and Core macros as well as modify those regions
Clock assignments
- Assign nets to clocks
- Assign global clock constraints to global, quadrant, and local clock resources
The Designer software enables you to set some advanced design-specific netlist optimizing constraints.
You can apply netlist optimization constraints to:
Delete or restore a buffer tree
Manage the fan-outs of the nets
Manage macro combinations (for example, IO-REG combining)
Optimize a netlist by removing buffers and/or inverters, propagating constants, and so on