The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:
|
Families |
SDC |
GCF |
DCF |
Timer/SmartTime |
|
Fusion |
X |
|
|
X |
|
ProASIC3E |
X |
|
|
X |
|
ProASIC3 |
X |
|
|
X |
|
ProASIC PLUS |
X |
|
|
X |
|
Axcelerator |
X |
|
|
X |
|
ProASIC |
X* |
X** |
|
X |
|
eX |
X*** |
|
X |
X |
|
SX-A |
X*** |
|
X |
X |
|
SX |
|
|
X |
X |
|
MX |
|
|
X |
X |
|
3200DX |
|
|
X |
X |
|
ACT3 |
|
|
X |
X |
|
ACT2/1200XL |
|
|
X |
X |
|
ACT1 |
|
|
X |
X |
(*) Supported for analysis only.
(**) Supported for layout only.
(***) the -through option is not supported for layout.
Use this constraint to set the maximum delay exception between the specified ports on a path.
You can set maximum delay exception in an SDC file, which you can either create yourself or generate with Synthesis tools, at the same time you import the netlist. Alternatively, you can set maximum delay exceptions using the GUI tools in the Designer software when you implement your design.
You can use one or more of the following commands or GUI tools to set maximum delay exception constraints:
SDC - set_max_delay
GCF - set_max_path_delay (backwards compatible for ProASIC families only)
DCF - pin_loads, max_delays
Timer - Paths tab
SmartTime - Specifying maximum delay constraint