The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:
|
Families |
SDC |
GCF |
Timer/SmartTime |
|
Fusion |
X |
|
X |
|
ProASIC3E |
X |
|
X |
|
ProASIC3 |
X |
|
X |
|
ProASIC PLUS |
X |
|
X |
|
Axcelerator |
X |
|
X |
|
ProASIC |
X* |
X** |
X |
|
eX |
X* |
|
X |
|
SX-A |
X* |
|
X |
|
SX |
|
|
|
|
MX |
|
|
|
|
3200DX |
|
|
|
|
ACT3 |
|
|
|
|
ACT2/1200XL |
|
|
|
|
ACT1 |
|
|
|
(*) Supported for analysis only.
(**) Supported for layout only.
Use this constraint to identify paths in the design that take multiple clock cycles.
You can set multicycle path constraints in an SDC file, which you can either create yourself or generate with Synthesis tools, at the same time you import the netlist. Alternatively, you can set multicycle paths using the GUI tools in the Designer software when you implement your design.
You can use one or more of the following commands or GUI tools to set multicycle paths constraints:
SDC - set_multicycle_path
GCF - set_multicycle_path (backwards compatible for ProASIC family only)
SmartTime - Specifying input delay constraint