Defines a path that takes multiple clock cycles.
set_multicycle_path ncycles [-from from_list] [–through through_list] [-to to_list]
ncycles
Specifies an integer value that represents a number of cycles the data path must have for setup or hold check. The value is relative to the starting point or ending point clock, before data is required at the ending point.
-from from_list
Specifies a list of timing path starting points. A valid timing starting point is a clock, a primary input, an inout port, or a clock pin of a sequential cell.
-through through_list
Specifies a list of pins or ports through which the multiple cycle paths must pass.
-to to_list
Specifies a list of timing path ending points. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.
set_multicycle_path 3 -from [get_pins {reg1}] –to [get_pins {reg2}]
SDC allows multiple priority management on the multiple cycle path constraint depending on the scope of the object accessors. In Actel design implementation, such priority management is not supported. All multiple cycle path constraints are handled with the same priority.