A clock conditioning circuit (CCC) can include any of the following functional block cores: CLKBUF, CLKINT, PLL, and CLKDLY. All of the CCCs include the quadrant clock feature.
You can use both CLKBUF and CLKINT as a quadrant clock driver. They can be placed in either a global or quadrant clock location.
The PLL and CLKDLY cores are options for a global or quadrant clock location.
You can instantiate as many CCC cores as you want in your design, up to the maximum allowed by the architecture (18).
Synthesis tools can only infer CLKBUF and CLKINT cores up to a total of six clocks in the design. The six clocks include any clock you instantiated using CCC cores. There is no user variable to control the maximum number of clocks available to the synthesis engines for inferring purposes.
If quadrant clocks are present in a design or if it is necessary to “promote” global clocks (CLKBUF, CLKINT, PLL, CLKDLY) to quadrant clocks to satisfy the clock network resource constraints, you must define physical design constraints to execute the promotion. You may choose to create physical design constraints using PDC commands (pre-compile) or the MVN interface (post-compile).
The advantage of using the PDC flow over the MVN flow is that Compile is able to automatically promote any regular net to a global net before assigning it to a quadrant.
The prelayout checker performs the following DRC checks:
The remaining clocks, which need to be assigned to a global clock resource, need to be less than 6. For example:
Resource Limit
The number of chip globals in your design exceeded the maximum number
available in the device.
The checker verifies that the total number of clock resources assigned to the given quadrant does not exceed 3. For example:
PRL09: The number of clocks assigned (4) to the Upper Left quadrant exceeds the maximum number available (3) in the device.
If a clock is placed and assigned to a quadrant clock region, the checker verifies that the clock is placed in the given quadrant clock region. For example:
PRL11: Cannot assign net:net_out2 to the Upper Right quadrant and its driver macro:clkbibuf1 to Upper Left quadrant which is outside the quadrant.
The clock placer places the quadrant clock based on your quadrant clock region assignment and also creates the quadrant clock region (if necessary).
If it fails to create the quadrant clock region for other constraints, then it repots an error and the flow stops. For example:
WARNING: macro and2 on net net_out2 cannot be assigned to region Qclk_net_out2. IsAssignmentLegal fails msg:
ERROR: Failed to create the region Qclk_net_out2.
ERROR: Failed in placing and fixing clock macros
ERROR: PLL/CLK Pre-Placer failed.