About Physical Design Constraint (PDC) Files

A PDC file is a Tcl script file specifying physical constraints. This file can be imported and exported from Designer. Any constraint that you can enter using the PinEditor in MVN or ChipPlanner tool, you can also use in a PDC file.

Note: Only Fusion, ProASIC3/E and Axcelerator devices support PDC files.

Designer supports the following PDC commands.

Command	Action
assign_global_clock	Assigns regular nets to global clock networks by promoting the net using a CLKINT macro
assign_local_clock	Assigns regular nets to local clock routing (Axcelerator) or to LocalClock regions (Fusion and ProASIC3/E)
assign_net_macros	Assigns the macros connected to a net to a specified defined region
assign_quadrant_clock	Assigns regular nets to a specific quadrant clock region (Fusion and ProASIC3/E)
assign_region	Assigns macros to a pre-specified region
define_region	Defines either a rectangular or rectilinear region
delete_buffer_tree	Removes all buffers and inverters from a given net for Fusion, ProASIC3 and ProASIC3E devices
dont_touch_buffer_tree	Restores all buffers and inverters that were removed from a given net with the delete_buffer_tree command
move_region	Moves a region to new coordinates
reset_floorplan	Deletes all defined regions. Placed macros are not affected
reset_io	Resets all attributes on a macro to the default values
reset_iobank	Resets an I/O banks technology to the default technology
reset_net_critical	Resets net criticality to default level
set_io	Sets the attributes of an I/O
set_iobank	Specifies the I/O bank’s technology
set_location	Places a given logic instance at a particular location
set_multitile_location	Assigns specified two-tile and four-tile macros to specified locations on the chip
set_net_critical	Sets net criticality, which is issued to influence placement and routing in favor of performance
set_vref	Specifies which pins are VREF pins
set_vref_defaults	Sets the default VREF pins for specified banks
unassign_global_clock	Assigns clock nets to regular nets
unassign_local_clock	Unassigns the specified user-defined net from a LocalClock or QuadrantClock region
unassign_macro_from_region	Unassigns macros from a specified region, if they are assigned to that region
unassign_net_macro	Unassigns macros connected to a specified net from a defined region
unassign_quadrant_clock	Unassigns the specified net from a QuadrantClock region
undefine_region	Removes the specified region

Note: PDC commands are case sensitive. However, their arguments are not.

About Physical Design Constraint (PDC) Files

See Also