Project sources are any design files that make up your design. These can include schematics, HDL files, simulation files, testbenches, etc. Anything that describes your design or is needed to program the device is a project source.
Source files appear in the Design Flow window. The Design Hierarchy tab displays the structure of the design modules as they relate to each other, while the File Manager tab displays all the files that make up the project.
The design description for a project is contained within the following types of sources:
Schematics
HDL Files (VHDL or Verilog)
One source file in the project is the top-level source for the design. The top-level source defines the inputs and outputs that will be mapped into the devices, and references the logic descriptions contained in lower-level sources. The referencing of another source is called an instantiation. Lower-level sources can also instantiate sources to build as many levels of logic as necessary to describe your design.
Some projects, like the CoreConsole project, require that you use the HDL Editor or ViewDraw to instantiate them. If you use the template created by CoreConsole to instantiate the top level of the CoreConsole project, you must create a new HDL source file and copy the content of the template. If you do not, Libero IDE overwrites the file if you re-import a CoreConsole project.
Some project sources can be imported.
Sources for your project can include:
|
Source |
File Extension |
|
Schematic |
*.1-9 |
|
Verilog Module |
.v |
|
VHDL Entity |
.vhd |
|
SmartGen Macro |
.gen |
|
Testbench |
.vhd |
|
Stimulus |
.tim |
|
Programming Files |
.afm, .prb |