The timing report contains the following sections:
The header lists:
The report type
The version of Designer used to generate the report
The date and time the report was generated
General design information (name, family, etc.)
The summary section reports the timing information for each clock domain. For example:
Clock Domain: SDRCLK_FPGA
Period (ns): 6.522
Frequency (MHz): 153.327
Required Period (ns): N/A
Required Frequency (MHz): N/A
External Setup (ns):
External Hold (ns):
Min Clock-To-Out (ns):
Max Clock-To-Out (ns):
The required period and frequency are available if a clock constraint has been defined for that domain.
By default, the clock domains reported are the explicit clock domains that are shown in SmartTime. You can filter the domains and get only specific sections in the report (see Timing Report Options).
The paths section lists the timing information for different types of paths in the design. This section is reported by default. You can deselect this option in the Timing Report Options dialog box.
By default, the number of paths displayed per set is 5.
You can filter the domains using the Timing Report Options dialog box.
You can also view the stored filter sets in the generated report using the timing report options (see Timing Report Options). The filter sets are listed by name in their appropriate section, and the number of paths reported for the filter set is the same as for the main sets.
By default, the filter sets are not reported.
The paths are organized by clock domain.
This set reports the paths from the registers clock pins to the registers data pins in the current clock domain.
This set reports the paths from the top level design input ports to the registers in the current clock domain.
This set reports the paths from the registers clock pins to the top level design output ports in the current clock domain.
This set reports the paths from the registers clock pins of the specified clock domain to the registers data pins in the current clock domain. Inter-domain paths are not reported by default.
This set lists input to output paths and user sets. Input to output paths are reported by default. To see the user-defined sets, use the Timing Report Options dialog box.
This set reports the paths from the top level design input ports to top level design output ports.
Expanded paths can be reported for each set. By default, the number of expanded paths to report is set to 1. You can select and change the number when you specify Timing Report Options.