Timing constraints overview

Timing constraints define the performance goals that drive the design implementation flow.

{Review the following old topic content.}

Timing constraints can be entered using the interactive Timer tool or by importing a constraint file.

To understand the complexity of a design and its performance, perform place-and-route with no constraints to see if routing can complete without constraints. If routing completes successfully, you can open Timer to see if the physical design meets timing requirements.  

ProASIC only: If you are using a synthesis tool such as Synopsys Design Compiler, Actel recommends that you use it to generate a forward SDF file containing path constraints only.

Over constraining a design may result in increased place-and-route run times, while not improving design performance.