Synopsys Design Constraints (SDC) is a Tcl based format used by Synopsys tools to specify the design intent, including the timing and area constraints for a design. Actel tools use a subset of the SDC format to capture supported timing constraints. You can import or export an SDC file from the Designer software. Any timing constraint that you can enter using Designer tools, can also be specified in an SDC file.
Use the SDC-based flow to share timing constraint information between Actel tools and third-party EDA tools.
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Command |
Action |
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Creates a clock and defines its characteristics |
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Creates an internally generated clock and defines its characteristics | |
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Identifies paths that are to be considered false and excluded from the timing analysis |
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Defines the arrival time of an input relative to a clock | |
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Sets the load to a specified value on a specified port | |
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Specifies the maximum delay for the timing paths | |
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Defines a path that takes multiple clock cycles | |
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Defines the output delay of an output relative to a clock |