/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
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/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)addr_tlb.v
***
***
*** Description:
*** Implements the afx address mapping and translating to pci space.
***
****************************************************************************
****************************************************************************/
module addr_tlb
(
pa_hold,
smbar0,
smbar1,
sibar,
msize0,
msize1,
pmbar0,
pmbar1,
pibar,
isize,
low_word_en,
any_hi_word_en,
config_add_31,
io_space_en,
mem_space_en,
config_add_en,
config_data_en,
falcon_reg_en,
special_cycle_en,
interrupt_ack_en,
boot_mode,
bm_sel,
pci_addr
);
// Port declarations
input [27:3] pa_hold
; // latched physical address
// from configuration registers
input [3:0] smbar0
; // relocation register 0 - top priority
input [3:0] smbar1
; // relocation register 0 - second priority
input [3:0] sibar
; // io relocation register - last priority
input [3:0] msize0
; // memory relocation size for smbar0
input [3:0] msize1
; // memory relocation size for smbar1
input [3:0] isize
; // memory relocation size for io
input [7:0] pmbar0
; // pci memory base reg0
input [7:0] pmbar1
; // pci memory base reg1
input [7:0] pibar
; // pci io base reg
input low_word_en
; // byte marks low word only - entire wd
input any_hi_word_en
; // byte marks hi word only - any byte
input config_add_31
; // enable io access to config data reg
input boot_mode
; // processor boot_mode
input [1:0] bm_sel
; // boot mode select
output io_space_en
; // io_space 64K fixed
output mem_space_en
; // mem_space
output config_add_en
; // configuration address enable
output config_data_en
; // configuration data enable
output falcon_reg_en
; // falcon register enable
output interrupt_ack_en
; // PCI special cycle enable
output special_cycle_en
; // PCI special cycle enable
output [31:3] pci_addr
; // address out to fifos
wire memaddr_match0
;
wire memaddr_match1
;
wire ioaddr_match
;
wire [31:3] pci_addr_dec
= pci_addr_gen(pa_hold, msize0, msize1, isize, pmbar0,
pmbar1, pibar, memaddr_match0, memaddr_match1, ioaddr_match) ;
wire pci_boot_cheerio
= boot_mode & (bm_sel == 2'h2);
wire pci_boot_superio
= boot_mode & (bm_sel == 2'h3);
// change to just use pa_hold for 2.0
//wire [31:3] cheerio_addr = {8'hf0, pci_addr_dec[23:3]};
//wire [31:3] superio_addr = {15'h7fff, pci_addr_dec[16:3]};
wire [31:3] cheerio_addr
= {8'hf0, pa_hold[23:3]};
wire [31:3] superio_addr
= {15'h7fff, pa_hold[16:3]};
wire [31:3] pci_addr = pci_boot_cheerio ? cheerio_addr :
pci_boot_superio ? superio_addr : pci_addr_dec[31:3];
wire fixed_map
= (pa_hold[27:24]==4'b0000) ;
wire pa_23_20_not_0
= (|pa_hold[23:20]) ;
wire [31:3] pass_thru_addr
= {4'b0,pa_hold[27:3]} ;
// translation can only occur when not in fixed map mode!
assign memaddr_match0 = ~fixed_map
& ((pa_hold[27:24] & msize0) == (smbar0[3:0] & msize0));
assign memaddr_match1 = ~fixed_map
& ((pa_hold[27:24] & msize1) == (smbar1[3:0] & msize1));
assign ioaddr_match = ~fixed_map
& ((pa_hold[27:24] & isize) == (sibar[3:0] & isize));
wire io_config_add_en
, io_config_data_en
;
// io space only when not accessing the config address register at
// address 0cf8 or the config data register at 0cfc
// OR access via the sibar translation
// OR the first 64K
wire io_space_en = (pa_hold[27:19] == 0) & ~(io_config_add_en
| io_config_data_en) | ioaddr_match & ~memaddr_match0 & ~memaddr_match1;
// memory space whenever bits 27:20 are:(XXXX is non-zero), (xxxx is don't care)
// 0000 XXXX,
// XXXX xxxx and no iomatch only
// xxxx XXXX and no iomatch only
wire mem_space_en = fixed_map & pa_23_20_not_0 | (~fixed_map | pa_23_20_not_0)
& ~(~memaddr_match0 & ~memaddr_match1 & ioaddr_match);
assign io_config_add_en =(pa_hold[27:19] == 0) & (pa_hold[18:3] == 16'h019f)
& low_word_en;
wire config_add_en = (pa_hold[27:17] == 11'h004) | io_config_add_en;
assign io_config_data_en =(pa_hold[27:19] == 0) & (pa_hold[18:3] == 16'h019f)
& any_hi_word_en & config_add_31;
wire config_data_en = (pa_hold[27:17] == 11'h005) | io_config_data_en;
wire falcon_reg_en = (pa_hold[27:17] == 11'h006);
wire special_cycle_en = (pa_hold[27:16] == 12'h00e);
wire interrupt_ack_en = (pa_hold[27:16] == 12'h00f);
function [31:3] pci_addr_gen ;
input [27:3] pa_hold;
input [3:0] msize0, msize1, isize ;
input [7:0] pmbar0, pmbar1, pibar ;
input memaddr_match0, memaddr_match1, ioaddr_match;
reg [31:3] temp_pci_addr ;
begin
casex (fixed_map)
1'b1: temp_pci_addr = pass_thru_addr;
// Change below so that the simbars actually map the range specified by
// msize. This is a 2.0 fix.
1'b0:
begin // TRANSLATE ADDRESS
casex ({memaddr_match0,memaddr_match1,ioaddr_match})
3'b1xx: temp_pci_addr = {pmbar0[7:4],
// ((smbar0[3:0] & msize0[3:0]) | pmbar0[3:0]),
((pa_hold[27:24] & ~msize0[3:0]) | pmbar0[3:0]),
pa_hold[23:3]} ;
3'b01x: temp_pci_addr = {pmbar1[7:4],
// ((smbar1[3:0] & msize1[3:0]) | pmbar1[3:0]),
((pa_hold[27:24] & ~msize1[3:0]) | pmbar1[3:0]),
pa_hold[23:3]} ;
3'b001: temp_pci_addr = {pibar[7:4],
// ((sibar[3:0] & isize[3:0]) | pibar[3:0]),
((pa_hold[27:24] & ~isize[3:0]) | pibar[3:0]),
pa_hold[23:3]} ;
default: temp_pci_addr = pass_thru_addr ;
endcase
end
default: temp_pci_addr = 28'habababa;
endcase
pci_addr_gen = temp_pci_addr ;
end
endfunction
endmodule
This page: |
Created: | Thu Aug 19 11:57:20 1999 |
| From: |
../../../sparc_v8/ssparc/pcic/afx_slave/rtl/addr_tlb.v
|